1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __FLOWCTRL_H__ 8 #define __FLOWCTRL_H__ 9 10 #include <mmio.h> 11 #include <tegra_def.h> 12 13 #define FLOWCTRL_HALT_CPU0_EVENTS 0x0U 14 #define FLOWCTRL_WAITEVENT (2U << 29) 15 #define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29) 16 #define FLOWCTRL_JTAG_RESUME (1U << 28) 17 #define FLOWCTRL_HALT_SCLK (1U << 27) 18 #define FLOWCTRL_HALT_LIC_IRQ (1U << 11) 19 #define FLOWCTRL_HALT_LIC_FIQ (1U << 10) 20 #define FLOWCTRL_HALT_GIC_IRQ (1U << 9) 21 #define FLOWCTRL_HALT_GIC_FIQ (1U << 8) 22 #define FLOWCTRL_HALT_BPMP_EVENTS 0x4U 23 #define FLOWCTRL_CPU0_CSR 0x8U 24 #define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16) 25 #define FLOWCTRL_CSR_INTR_FLAG (1U << 15) 26 #define FLOWCTRL_CSR_EVENT_FLAG (1U << 14) 27 #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3) 28 #define FLOWCTRL_CSR_ENABLE (1U << 0) 29 #define FLOWCTRL_HALT_CPU1_EVENTS 0x14U 30 #define FLOWCTRL_CPU1_CSR 0x18U 31 #define FLOWCTRL_CC4_CORE0_CTRL 0x6cU 32 #define FLOWCTRL_WAIT_WFI_BITMAP 0x100U 33 #define FLOWCTRL_L2_FLUSH_CONTROL 0x94U 34 #define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U 35 #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2) 36 37 #define FLOWCTRL_ENABLE_EXT 12U 38 #define FLOWCTRL_ENABLE_EXT_MASK 3U 39 #define FLOWCTRL_PG_CPU_NONCPU 0x1U 40 #define FLOWCTRL_TURNOFF_CPURAIL 0x2U 41 42 static inline uint32_t tegra_fc_read_32(uint32_t off) 43 { 44 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); 45 } 46 47 static inline void tegra_fc_write_32(uint32_t off, uint32_t val) 48 { 49 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); 50 } 51 52 void tegra_fc_cluster_idle(uint32_t midr); 53 void tegra_fc_cpu_powerdn(uint32_t mpidr); 54 void tegra_fc_cluster_powerdn(uint32_t midr); 55 void tegra_fc_soc_powerdn(uint32_t midr); 56 void tegra_fc_cpu_on(int cpu); 57 void tegra_fc_cpu_off(int cpu); 58 void tegra_fc_lock_active_cluster(void); 59 void tegra_fc_reset_bpmp(void); 60 61 #endif /* __FLOWCTRL_H__ */ 62
