1 // Copyright 2015, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_ 28 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_ 29 30 #include "../globals-vixl.h" 31 32 namespace vixl { 33 namespace aarch64 { 34 35 const unsigned kNumberOfRegisters = 32; 36 const unsigned kNumberOfVRegisters = 32; 37 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters; 38 // Callee saved registers are x21-x30(lr). 39 const int kNumberOfCalleeSavedRegisters = 10; 40 const int kFirstCalleeSavedRegisterIndex = 21; 41 // Callee saved FP registers are d8-d15. 42 const int kNumberOfCalleeSavedFPRegisters = 8; 43 const int kFirstCalleeSavedFPRegisterIndex = 8; 44 45 // clang-format off 46 #define AARCH64_REGISTER_CODE_LIST(R) \ 47 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 48 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 49 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 50 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 51 52 #define INSTRUCTION_FIELDS_LIST(V_) \ 53 /* Register fields */ \ 54 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \ 55 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \ 56 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \ 57 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \ 58 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \ 59 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \ 60 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \ 61 \ 62 /* Common bits */ \ 63 V_(SixtyFourBits, 31, 31, ExtractBits) \ 64 V_(FlagsUpdate, 29, 29, ExtractBits) \ 65 \ 66 /* PC relative addressing */ \ 67 V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \ 68 V_(ImmPCRelLo, 30, 29, ExtractBits) \ 69 \ 70 /* Add/subtract/logical shift register */ \ 71 V_(ShiftDP, 23, 22, ExtractBits) \ 72 V_(ImmDPShift, 15, 10, ExtractBits) \ 73 \ 74 /* Add/subtract immediate */ \ 75 V_(ImmAddSub, 21, 10, ExtractBits) \ 76 V_(ShiftAddSub, 23, 22, ExtractBits) \ 77 \ 78 /* Add/substract extend */ \ 79 V_(ImmExtendShift, 12, 10, ExtractBits) \ 80 V_(ExtendMode, 15, 13, ExtractBits) \ 81 \ 82 /* Move wide */ \ 83 V_(ImmMoveWide, 20, 5, ExtractBits) \ 84 V_(ShiftMoveWide, 22, 21, ExtractBits) \ 85 \ 86 /* Logical immediate, bitfield and extract */ \ 87 V_(BitN, 22, 22, ExtractBits) \ 88 V_(ImmRotate, 21, 16, ExtractBits) \ 89 V_(ImmSetBits, 15, 10, ExtractBits) \ 90 V_(ImmR, 21, 16, ExtractBits) \ 91 V_(ImmS, 15, 10, ExtractBits) \ 92 \ 93 /* Test and branch immediate */ \ 94 V_(ImmTestBranch, 18, 5, ExtractSignedBits) \ 95 V_(ImmTestBranchBit40, 23, 19, ExtractBits) \ 96 V_(ImmTestBranchBit5, 31, 31, ExtractBits) \ 97 \ 98 /* Conditionals */ \ 99 V_(Condition, 15, 12, ExtractBits) \ 100 V_(ConditionBranch, 3, 0, ExtractBits) \ 101 V_(Nzcv, 3, 0, ExtractBits) \ 102 V_(ImmCondCmp, 20, 16, ExtractBits) \ 103 V_(ImmCondBranch, 23, 5, ExtractSignedBits) \ 104 \ 105 /* Floating point */ \ 106 V_(FPType, 23, 22, ExtractBits) \ 107 V_(ImmFP, 20, 13, ExtractBits) \ 108 V_(FPScale, 15, 10, ExtractBits) \ 109 \ 110 /* Load Store */ \ 111 V_(ImmLS, 20, 12, ExtractSignedBits) \ 112 V_(ImmLSUnsigned, 21, 10, ExtractBits) \ 113 V_(ImmLSPair, 21, 15, ExtractSignedBits) \ 114 V_(ImmShiftLS, 12, 12, ExtractBits) \ 115 V_(LSOpc, 23, 22, ExtractBits) \ 116 V_(LSVector, 26, 26, ExtractBits) \ 117 V_(LSSize, 31, 30, ExtractBits) \ 118 V_(ImmPrefetchOperation, 4, 0, ExtractBits) \ 119 V_(PrefetchHint, 4, 3, ExtractBits) \ 120 V_(PrefetchTarget, 2, 1, ExtractBits) \ 121 V_(PrefetchStream, 0, 0, ExtractBits) \ 122 \ 123 /* Other immediates */ \ 124 V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \ 125 V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \ 126 V_(ImmLLiteral, 23, 5, ExtractSignedBits) \ 127 V_(ImmException, 20, 5, ExtractBits) \ 128 V_(ImmHint, 11, 5, ExtractBits) \ 129 V_(ImmBarrierDomain, 11, 10, ExtractBits) \ 130 V_(ImmBarrierType, 9, 8, ExtractBits) \ 131 \ 132 /* System (MRS, MSR, SYS) */ \ 133 V_(ImmSystemRegister, 20, 5, ExtractBits) \ 134 V_(SysO0, 19, 19, ExtractBits) \ 135 V_(SysOp, 18, 5, ExtractBits) \ 136 V_(SysOp0, 20, 19, ExtractBits) \ 137 V_(SysOp1, 18, 16, ExtractBits) \ 138 V_(SysOp2, 7, 5, ExtractBits) \ 139 V_(CRn, 15, 12, ExtractBits) \ 140 V_(CRm, 11, 8, ExtractBits) \ 141 \ 142 /* Load-/store-exclusive */ \ 143 V_(LdStXLoad, 22, 22, ExtractBits) \ 144 V_(LdStXNotExclusive, 23, 23, ExtractBits) \ 145 V_(LdStXAcquireRelease, 15, 15, ExtractBits) \ 146 V_(LdStXSizeLog2, 31, 30, ExtractBits) \ 147 V_(LdStXPair, 21, 21, ExtractBits) \ 148 \ 149 /* NEON generic fields */ \ 150 V_(NEONQ, 30, 30, ExtractBits) \ 151 V_(NEONSize, 23, 22, ExtractBits) \ 152 V_(NEONLSSize, 11, 10, ExtractBits) \ 153 V_(NEONS, 12, 12, ExtractBits) \ 154 V_(NEONL, 21, 21, ExtractBits) \ 155 V_(NEONM, 20, 20, ExtractBits) \ 156 V_(NEONH, 11, 11, ExtractBits) \ 157 V_(ImmNEONExt, 14, 11, ExtractBits) \ 158 V_(ImmNEON5, 20, 16, ExtractBits) \ 159 V_(ImmNEON4, 14, 11, ExtractBits) \ 160 \ 161 /* NEON extra fields */ \ 162 V_(ImmRotFcadd, 12, 12, ExtractBits) \ 163 V_(ImmRotFcmlaVec, 12, 11, ExtractBits) \ 164 V_(ImmRotFcmlaSca, 14, 13, ExtractBits) \ 165 \ 166 /* NEON Modified Immediate fields */ \ 167 V_(ImmNEONabc, 18, 16, ExtractBits) \ 168 V_(ImmNEONdefgh, 9, 5, ExtractBits) \ 169 V_(NEONModImmOp, 29, 29, ExtractBits) \ 170 V_(NEONCmode, 15, 12, ExtractBits) \ 171 \ 172 /* NEON Shift Immediate fields */ \ 173 V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \ 174 V_(ImmNEONImmh, 22, 19, ExtractBits) \ 175 V_(ImmNEONImmb, 18, 16, ExtractBits) 176 // clang-format on 177 178 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 179 /* NZCV */ \ 180 V_(Flags, 31, 28, ExtractBits) \ 181 V_(N, 31, 31, ExtractBits) \ 182 V_(Z, 30, 30, ExtractBits) \ 183 V_(C, 29, 29, ExtractBits) \ 184 V_(V, 28, 28, ExtractBits) \ 185 M_(NZCV, Flags_mask) \ 186 /* FPCR */ \ 187 V_(AHP, 26, 26, ExtractBits) \ 188 V_(DN, 25, 25, ExtractBits) \ 189 V_(FZ, 24, 24, ExtractBits) \ 190 V_(RMode, 23, 22, ExtractBits) \ 191 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 192 193 // Fields offsets. 194 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ 195 const int Name##_offset = LowBit; \ 196 const int Name##_width = HighBit - LowBit + 1; \ 197 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 198 #define NOTHING(A, B) 199 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) 200 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 201 #undef NOTHING 202 #undef DECLARE_FIELDS_BITS 203 204 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 205 // from ImmPCRelLo and ImmPCRelHi. 206 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 207 208 // Disable `clang-format` for the `enum`s below. We care about the manual 209 // formatting that `clang-format` would destroy. 210 // clang-format off 211 212 // Condition codes. 213 enum Condition { 214 eq = 0, // Z set Equal. 215 ne = 1, // Z clear Not equal. 216 cs = 2, // C set Carry set. 217 cc = 3, // C clear Carry clear. 218 mi = 4, // N set Negative. 219 pl = 5, // N clear Positive or zero. 220 vs = 6, // V set Overflow. 221 vc = 7, // V clear No overflow. 222 hi = 8, // C set, Z clear Unsigned higher. 223 ls = 9, // C clear or Z set Unsigned lower or same. 224 ge = 10, // N == V Greater or equal. 225 lt = 11, // N != V Less than. 226 gt = 12, // Z clear, N == V Greater than. 227 le = 13, // Z set or N != V Less then or equal 228 al = 14, // Always. 229 nv = 15, // Behaves as always/al. 230 231 // Aliases. 232 hs = cs, // C set Unsigned higher or same. 233 lo = cc // C clear Unsigned lower. 234 }; 235 236 inline Condition InvertCondition(Condition cond) { 237 // Conditions al and nv behave identically, as "always true". They can't be 238 // inverted, because there is no "always false" condition. 239 VIXL_ASSERT((cond != al) && (cond != nv)); 240 return static_cast<Condition>(cond ^ 1); 241 } 242 243 enum FPTrapFlags { 244 EnableTrap = 1, 245 DisableTrap = 0 246 }; 247 248 enum FlagsUpdate { 249 SetFlags = 1, 250 LeaveFlags = 0 251 }; 252 253 enum StatusFlags { 254 NoFlag = 0, 255 256 // Derive the flag combinations from the system register bit descriptions. 257 NFlag = N_mask, 258 ZFlag = Z_mask, 259 CFlag = C_mask, 260 VFlag = V_mask, 261 NZFlag = NFlag | ZFlag, 262 NCFlag = NFlag | CFlag, 263 NVFlag = NFlag | VFlag, 264 ZCFlag = ZFlag | CFlag, 265 ZVFlag = ZFlag | VFlag, 266 CVFlag = CFlag | VFlag, 267 NZCFlag = NFlag | ZFlag | CFlag, 268 NZVFlag = NFlag | ZFlag | VFlag, 269 NCVFlag = NFlag | CFlag | VFlag, 270 ZCVFlag = ZFlag | CFlag | VFlag, 271 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 272 273 // Floating-point comparison results. 274 FPEqualFlag = ZCFlag, 275 FPLessThanFlag = NFlag, 276 FPGreaterThanFlag = CFlag, 277 FPUnorderedFlag = CVFlag 278 }; 279 280 enum Shift { 281 NO_SHIFT = -1, 282 LSL = 0x0, 283 LSR = 0x1, 284 ASR = 0x2, 285 ROR = 0x3, 286 MSL = 0x4 287 }; 288 289 enum Extend { 290 NO_EXTEND = -1, 291 UXTB = 0, 292 UXTH = 1, 293 UXTW = 2, 294 UXTX = 3, 295 SXTB = 4, 296 SXTH = 5, 297 SXTW = 6, 298 SXTX = 7 299 }; 300 301 enum SystemHint { 302 NOP = 0, 303 YIELD = 1, 304 WFE = 2, 305 WFI = 3, 306 SEV = 4, 307 SEVL = 5, 308 ESB = 16, 309 CSDB = 20 310 }; 311 312 enum BarrierDomain { 313 OuterShareable = 0, 314 NonShareable = 1, 315 InnerShareable = 2, 316 FullSystem = 3 317 }; 318 319 enum BarrierType { 320 BarrierOther = 0, 321 BarrierReads = 1, 322 BarrierWrites = 2, 323 BarrierAll = 3 324 }; 325 326 enum PrefetchOperation { 327 PLDL1KEEP = 0x00, 328 PLDL1STRM = 0x01, 329 PLDL2KEEP = 0x02, 330 PLDL2STRM = 0x03, 331 PLDL3KEEP = 0x04, 332 PLDL3STRM = 0x05, 333 334 PLIL1KEEP = 0x08, 335 PLIL1STRM = 0x09, 336 PLIL2KEEP = 0x0a, 337 PLIL2STRM = 0x0b, 338 PLIL3KEEP = 0x0c, 339 PLIL3STRM = 0x0d, 340 341 PSTL1KEEP = 0x10, 342 PSTL1STRM = 0x11, 343 PSTL2KEEP = 0x12, 344 PSTL2STRM = 0x13, 345 PSTL3KEEP = 0x14, 346 PSTL3STRM = 0x15 347 }; 348 349 template<int op0, int op1, int crn, int crm, int op2> 350 class SystemRegisterEncoder { 351 public: 352 static const uint32_t value = 353 ((op0 << SysO0_offset) | 354 (op1 << SysOp1_offset) | 355 (crn << CRn_offset) | 356 (crm << CRm_offset) | 357 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset; 358 }; 359 360 // System/special register names. 361 // This information is not encoded as one field but as the concatenation of 362 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). 363 enum SystemRegister { 364 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, 365 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value 366 }; 367 368 template<int op1, int crn, int crm, int op2> 369 class CacheOpEncoder { 370 public: 371 static const uint32_t value = 372 ((op1 << SysOp1_offset) | 373 (crn << CRn_offset) | 374 (crm << CRm_offset) | 375 (op2 << SysOp2_offset)) >> SysOp_offset; 376 }; 377 378 enum InstructionCacheOp { 379 IVAU = CacheOpEncoder<3, 7, 5, 1>::value 380 }; 381 382 enum DataCacheOp { 383 CVAC = CacheOpEncoder<3, 7, 10, 1>::value, 384 CVAU = CacheOpEncoder<3, 7, 11, 1>::value, 385 CIVAC = CacheOpEncoder<3, 7, 14, 1>::value, 386 ZVA = CacheOpEncoder<3, 7, 4, 1>::value 387 }; 388 389 // Instruction enumerations. 390 // 391 // These are the masks that define a class of instructions, and the list of 392 // instructions within each class. Each enumeration has a Fixed, FMask and 393 // Mask value. 394 // 395 // Fixed: The fixed bits in this instruction class. 396 // FMask: The mask used to extract the fixed bits in the class. 397 // Mask: The mask used to identify the instructions within a class. 398 // 399 // The enumerations can be used like this: 400 // 401 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 402 // switch(instr->Mask(PCRelAddressingMask)) { 403 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 404 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 405 // default: printf("Unknown instruction\n"); 406 // } 407 408 409 // Generic fields. 410 enum GenericInstrField { 411 SixtyFourBits = 0x80000000, 412 ThirtyTwoBits = 0x00000000, 413 414 FPTypeMask = 0x00C00000, 415 FP16 = 0x00C00000, 416 FP32 = 0x00000000, 417 FP64 = 0x00400000 418 }; 419 420 enum NEONFormatField { 421 NEONFormatFieldMask = 0x40C00000, 422 NEON_Q = 0x40000000, 423 NEON_8B = 0x00000000, 424 NEON_16B = NEON_8B | NEON_Q, 425 NEON_4H = 0x00400000, 426 NEON_8H = NEON_4H | NEON_Q, 427 NEON_2S = 0x00800000, 428 NEON_4S = NEON_2S | NEON_Q, 429 NEON_1D = 0x00C00000, 430 NEON_2D = 0x00C00000 | NEON_Q 431 }; 432 433 enum NEONFPFormatField { 434 NEONFPFormatFieldMask = 0x40400000, 435 NEON_FP_4H = FP16, 436 NEON_FP_2S = FP32, 437 NEON_FP_8H = FP16 | NEON_Q, 438 NEON_FP_4S = FP32 | NEON_Q, 439 NEON_FP_2D = FP64 | NEON_Q 440 }; 441 442 enum NEONLSFormatField { 443 NEONLSFormatFieldMask = 0x40000C00, 444 LS_NEON_8B = 0x00000000, 445 LS_NEON_16B = LS_NEON_8B | NEON_Q, 446 LS_NEON_4H = 0x00000400, 447 LS_NEON_8H = LS_NEON_4H | NEON_Q, 448 LS_NEON_2S = 0x00000800, 449 LS_NEON_4S = LS_NEON_2S | NEON_Q, 450 LS_NEON_1D = 0x00000C00, 451 LS_NEON_2D = LS_NEON_1D | NEON_Q 452 }; 453 454 enum NEONScalarFormatField { 455 NEONScalarFormatFieldMask = 0x00C00000, 456 NEONScalar = 0x10000000, 457 NEON_B = 0x00000000, 458 NEON_H = 0x00400000, 459 NEON_S = 0x00800000, 460 NEON_D = 0x00C00000 461 }; 462 463 // PC relative addressing. 464 enum PCRelAddressingOp { 465 PCRelAddressingFixed = 0x10000000, 466 PCRelAddressingFMask = 0x1F000000, 467 PCRelAddressingMask = 0x9F000000, 468 ADR = PCRelAddressingFixed | 0x00000000, 469 ADRP = PCRelAddressingFixed | 0x80000000 470 }; 471 472 // Add/sub (immediate, shifted and extended.) 473 const int kSFOffset = 31; 474 enum AddSubOp { 475 AddSubOpMask = 0x60000000, 476 AddSubSetFlagsBit = 0x20000000, 477 ADD = 0x00000000, 478 ADDS = ADD | AddSubSetFlagsBit, 479 SUB = 0x40000000, 480 SUBS = SUB | AddSubSetFlagsBit 481 }; 482 483 #define ADD_SUB_OP_LIST(V) \ 484 V(ADD), \ 485 V(ADDS), \ 486 V(SUB), \ 487 V(SUBS) 488 489 enum AddSubImmediateOp { 490 AddSubImmediateFixed = 0x11000000, 491 AddSubImmediateFMask = 0x1F000000, 492 AddSubImmediateMask = 0xFF000000, 493 #define ADD_SUB_IMMEDIATE(A) \ 494 A##_w_imm = AddSubImmediateFixed | A, \ 495 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 496 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 497 #undef ADD_SUB_IMMEDIATE 498 }; 499 500 enum AddSubShiftedOp { 501 AddSubShiftedFixed = 0x0B000000, 502 AddSubShiftedFMask = 0x1F200000, 503 AddSubShiftedMask = 0xFF200000, 504 #define ADD_SUB_SHIFTED(A) \ 505 A##_w_shift = AddSubShiftedFixed | A, \ 506 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 507 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 508 #undef ADD_SUB_SHIFTED 509 }; 510 511 enum AddSubExtendedOp { 512 AddSubExtendedFixed = 0x0B200000, 513 AddSubExtendedFMask = 0x1F200000, 514 AddSubExtendedMask = 0xFFE00000, 515 #define ADD_SUB_EXTENDED(A) \ 516 A##_w_ext = AddSubExtendedFixed | A, \ 517 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 518 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 519 #undef ADD_SUB_EXTENDED 520 }; 521 522 // Add/sub with carry. 523 enum AddSubWithCarryOp { 524 AddSubWithCarryFixed = 0x1A000000, 525 AddSubWithCarryFMask = 0x1FE00000, 526 AddSubWithCarryMask = 0xFFE0FC00, 527 ADC_w = AddSubWithCarryFixed | ADD, 528 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 529 ADC = ADC_w, 530 ADCS_w = AddSubWithCarryFixed | ADDS, 531 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 532 SBC_w = AddSubWithCarryFixed | SUB, 533 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 534 SBC = SBC_w, 535 SBCS_w = AddSubWithCarryFixed | SUBS, 536 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 537 }; 538 539 540 // Logical (immediate and shifted register). 541 enum LogicalOp { 542 LogicalOpMask = 0x60200000, 543 NOT = 0x00200000, 544 AND = 0x00000000, 545 BIC = AND | NOT, 546 ORR = 0x20000000, 547 ORN = ORR | NOT, 548 EOR = 0x40000000, 549 EON = EOR | NOT, 550 ANDS = 0x60000000, 551 BICS = ANDS | NOT 552 }; 553 554 // Logical immediate. 555 enum LogicalImmediateOp { 556 LogicalImmediateFixed = 0x12000000, 557 LogicalImmediateFMask = 0x1F800000, 558 LogicalImmediateMask = 0xFF800000, 559 AND_w_imm = LogicalImmediateFixed | AND, 560 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 561 ORR_w_imm = LogicalImmediateFixed | ORR, 562 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 563 EOR_w_imm = LogicalImmediateFixed | EOR, 564 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 565 ANDS_w_imm = LogicalImmediateFixed | ANDS, 566 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 567 }; 568 569 // Logical shifted register. 570 enum LogicalShiftedOp { 571 LogicalShiftedFixed = 0x0A000000, 572 LogicalShiftedFMask = 0x1F000000, 573 LogicalShiftedMask = 0xFF200000, 574 AND_w = LogicalShiftedFixed | AND, 575 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 576 AND_shift = AND_w, 577 BIC_w = LogicalShiftedFixed | BIC, 578 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 579 BIC_shift = BIC_w, 580 ORR_w = LogicalShiftedFixed | ORR, 581 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 582 ORR_shift = ORR_w, 583 ORN_w = LogicalShiftedFixed | ORN, 584 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 585 ORN_shift = ORN_w, 586 EOR_w = LogicalShiftedFixed | EOR, 587 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 588 EOR_shift = EOR_w, 589 EON_w = LogicalShiftedFixed | EON, 590 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 591 EON_shift = EON_w, 592 ANDS_w = LogicalShiftedFixed | ANDS, 593 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 594 ANDS_shift = ANDS_w, 595 BICS_w = LogicalShiftedFixed | BICS, 596 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 597 BICS_shift = BICS_w 598 }; 599 600 // Move wide immediate. 601 enum MoveWideImmediateOp { 602 MoveWideImmediateFixed = 0x12800000, 603 MoveWideImmediateFMask = 0x1F800000, 604 MoveWideImmediateMask = 0xFF800000, 605 MOVN = 0x00000000, 606 MOVZ = 0x40000000, 607 MOVK = 0x60000000, 608 MOVN_w = MoveWideImmediateFixed | MOVN, 609 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 610 MOVZ_w = MoveWideImmediateFixed | MOVZ, 611 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 612 MOVK_w = MoveWideImmediateFixed | MOVK, 613 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 614 }; 615 616 // Bitfield. 617 const int kBitfieldNOffset = 22; 618 enum BitfieldOp { 619 BitfieldFixed = 0x13000000, 620 BitfieldFMask = 0x1F800000, 621 BitfieldMask = 0xFF800000, 622 SBFM_w = BitfieldFixed | 0x00000000, 623 SBFM_x = BitfieldFixed | 0x80000000, 624 SBFM = SBFM_w, 625 BFM_w = BitfieldFixed | 0x20000000, 626 BFM_x = BitfieldFixed | 0xA0000000, 627 BFM = BFM_w, 628 UBFM_w = BitfieldFixed | 0x40000000, 629 UBFM_x = BitfieldFixed | 0xC0000000, 630 UBFM = UBFM_w 631 // Bitfield N field. 632 }; 633 634 // Extract. 635 enum ExtractOp { 636 ExtractFixed = 0x13800000, 637 ExtractFMask = 0x1F800000, 638 ExtractMask = 0xFFA00000, 639 EXTR_w = ExtractFixed | 0x00000000, 640 EXTR_x = ExtractFixed | 0x80000000, 641 EXTR = EXTR_w 642 }; 643 644 // Unconditional branch. 645 enum UnconditionalBranchOp { 646 UnconditionalBranchFixed = 0x14000000, 647 UnconditionalBranchFMask = 0x7C000000, 648 UnconditionalBranchMask = 0xFC000000, 649 B = UnconditionalBranchFixed | 0x00000000, 650 BL = UnconditionalBranchFixed | 0x80000000 651 }; 652 653 // Unconditional branch to register. 654 enum UnconditionalBranchToRegisterOp { 655 UnconditionalBranchToRegisterFixed = 0xD6000000, 656 UnconditionalBranchToRegisterFMask = 0xFE000000, 657 UnconditionalBranchToRegisterMask = 0xFFFFFC00, 658 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 659 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 660 RET = UnconditionalBranchToRegisterFixed | 0x005F0000, 661 662 BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800, 663 BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00, 664 BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800, 665 BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00, 666 RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800, 667 RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00, 668 BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800, 669 BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00, 670 BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800, 671 BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00 672 }; 673 674 // Compare and branch. 675 enum CompareBranchOp { 676 CompareBranchFixed = 0x34000000, 677 CompareBranchFMask = 0x7E000000, 678 CompareBranchMask = 0xFF000000, 679 CBZ_w = CompareBranchFixed | 0x00000000, 680 CBZ_x = CompareBranchFixed | 0x80000000, 681 CBZ = CBZ_w, 682 CBNZ_w = CompareBranchFixed | 0x01000000, 683 CBNZ_x = CompareBranchFixed | 0x81000000, 684 CBNZ = CBNZ_w 685 }; 686 687 // Test and branch. 688 enum TestBranchOp { 689 TestBranchFixed = 0x36000000, 690 TestBranchFMask = 0x7E000000, 691 TestBranchMask = 0x7F000000, 692 TBZ = TestBranchFixed | 0x00000000, 693 TBNZ = TestBranchFixed | 0x01000000 694 }; 695 696 // Conditional branch. 697 enum ConditionalBranchOp { 698 ConditionalBranchFixed = 0x54000000, 699 ConditionalBranchFMask = 0xFE000000, 700 ConditionalBranchMask = 0xFF000010, 701 B_cond = ConditionalBranchFixed | 0x00000000 702 }; 703 704 // System. 705 // System instruction encoding is complicated because some instructions use op 706 // and CR fields to encode parameters. To handle this cleanly, the system 707 // instructions are split into more than one enum. 708 709 enum SystemOp { 710 SystemFixed = 0xD5000000, 711 SystemFMask = 0xFFC00000 712 }; 713 714 enum SystemSysRegOp { 715 SystemSysRegFixed = 0xD5100000, 716 SystemSysRegFMask = 0xFFD00000, 717 SystemSysRegMask = 0xFFF00000, 718 MRS = SystemSysRegFixed | 0x00200000, 719 MSR = SystemSysRegFixed | 0x00000000 720 }; 721 722 enum SystemHintOp { 723 SystemHintFixed = 0xD503201F, 724 SystemHintFMask = 0xFFFFF01F, 725 SystemHintMask = 0xFFFFF01F, 726 HINT = SystemHintFixed | 0x00000000 727 }; 728 729 enum SystemSysOp { 730 SystemSysFixed = 0xD5080000, 731 SystemSysFMask = 0xFFF80000, 732 SystemSysMask = 0xFFF80000, 733 SYS = SystemSysFixed | 0x00000000 734 }; 735 736 // Exception. 737 enum ExceptionOp { 738 ExceptionFixed = 0xD4000000, 739 ExceptionFMask = 0xFF000000, 740 ExceptionMask = 0xFFE0001F, 741 HLT = ExceptionFixed | 0x00400000, 742 BRK = ExceptionFixed | 0x00200000, 743 SVC = ExceptionFixed | 0x00000001, 744 HVC = ExceptionFixed | 0x00000002, 745 SMC = ExceptionFixed | 0x00000003, 746 DCPS1 = ExceptionFixed | 0x00A00001, 747 DCPS2 = ExceptionFixed | 0x00A00002, 748 DCPS3 = ExceptionFixed | 0x00A00003 749 }; 750 751 enum MemBarrierOp { 752 MemBarrierFixed = 0xD503309F, 753 MemBarrierFMask = 0xFFFFF09F, 754 MemBarrierMask = 0xFFFFF0FF, 755 DSB = MemBarrierFixed | 0x00000000, 756 DMB = MemBarrierFixed | 0x00000020, 757 ISB = MemBarrierFixed | 0x00000040 758 }; 759 760 enum SystemExclusiveMonitorOp { 761 SystemExclusiveMonitorFixed = 0xD503305F, 762 SystemExclusiveMonitorFMask = 0xFFFFF0FF, 763 SystemExclusiveMonitorMask = 0xFFFFF0FF, 764 CLREX = SystemExclusiveMonitorFixed 765 }; 766 767 enum SystemPAuthOp { 768 SystemPAuthFixed = 0xD503211F, 769 SystemPAuthFMask = 0xFFFFFD1F, 770 SystemPAuthMask = 0xFFFFFFFF, 771 PACIA1716 = SystemPAuthFixed | 0x00000100, 772 PACIB1716 = SystemPAuthFixed | 0x00000140, 773 AUTIA1716 = SystemPAuthFixed | 0x00000180, 774 AUTIB1716 = SystemPAuthFixed | 0x000001C0, 775 PACIAZ = SystemPAuthFixed | 0x00000300, 776 PACIASP = SystemPAuthFixed | 0x00000320, 777 PACIBZ = SystemPAuthFixed | 0x00000340, 778 PACIBSP = SystemPAuthFixed | 0x00000360, 779 AUTIAZ = SystemPAuthFixed | 0x00000380, 780 AUTIASP = SystemPAuthFixed | 0x000003A0, 781 AUTIBZ = SystemPAuthFixed | 0x000003C0, 782 AUTIBSP = SystemPAuthFixed | 0x000003E0, 783 784 // XPACLRI has the same fixed mask as System Hints and needs to be handled 785 // differently. 786 XPACLRI = 0xD50320FF 787 }; 788 789 // Any load or store. 790 enum LoadStoreAnyOp { 791 LoadStoreAnyFMask = 0x0a000000, 792 LoadStoreAnyFixed = 0x08000000 793 }; 794 795 // Any load pair or store pair. 796 enum LoadStorePairAnyOp { 797 LoadStorePairAnyFMask = 0x3a000000, 798 LoadStorePairAnyFixed = 0x28000000 799 }; 800 801 #define LOAD_STORE_PAIR_OP_LIST(V) \ 802 V(STP, w, 0x00000000), \ 803 V(LDP, w, 0x00400000), \ 804 V(LDPSW, x, 0x40400000), \ 805 V(STP, x, 0x80000000), \ 806 V(LDP, x, 0x80400000), \ 807 V(STP, s, 0x04000000), \ 808 V(LDP, s, 0x04400000), \ 809 V(STP, d, 0x44000000), \ 810 V(LDP, d, 0x44400000), \ 811 V(STP, q, 0x84000000), \ 812 V(LDP, q, 0x84400000) 813 814 // Load/store pair (post, pre and offset.) 815 enum LoadStorePairOp { 816 LoadStorePairMask = 0xC4400000, 817 LoadStorePairLBit = 1 << 22, 818 #define LOAD_STORE_PAIR(A, B, C) \ 819 A##_##B = C 820 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 821 #undef LOAD_STORE_PAIR 822 }; 823 824 enum LoadStorePairPostIndexOp { 825 LoadStorePairPostIndexFixed = 0x28800000, 826 LoadStorePairPostIndexFMask = 0x3B800000, 827 LoadStorePairPostIndexMask = 0xFFC00000, 828 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 829 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 830 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 831 #undef LOAD_STORE_PAIR_POST_INDEX 832 }; 833 834 enum LoadStorePairPreIndexOp { 835 LoadStorePairPreIndexFixed = 0x29800000, 836 LoadStorePairPreIndexFMask = 0x3B800000, 837 LoadStorePairPreIndexMask = 0xFFC00000, 838 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 839 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 840 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 841 #undef LOAD_STORE_PAIR_PRE_INDEX 842 }; 843 844 enum LoadStorePairOffsetOp { 845 LoadStorePairOffsetFixed = 0x29000000, 846 LoadStorePairOffsetFMask = 0x3B800000, 847 LoadStorePairOffsetMask = 0xFFC00000, 848 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 849 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 850 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 851 #undef LOAD_STORE_PAIR_OFFSET 852 }; 853 854 enum LoadStorePairNonTemporalOp { 855 LoadStorePairNonTemporalFixed = 0x28000000, 856 LoadStorePairNonTemporalFMask = 0x3B800000, 857 LoadStorePairNonTemporalMask = 0xFFC00000, 858 LoadStorePairNonTemporalLBit = 1 << 22, 859 STNP_w = LoadStorePairNonTemporalFixed | STP_w, 860 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, 861 STNP_x = LoadStorePairNonTemporalFixed | STP_x, 862 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, 863 STNP_s = LoadStorePairNonTemporalFixed | STP_s, 864 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, 865 STNP_d = LoadStorePairNonTemporalFixed | STP_d, 866 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d, 867 STNP_q = LoadStorePairNonTemporalFixed | STP_q, 868 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q 869 }; 870 871 // Load literal. 872 enum LoadLiteralOp { 873 LoadLiteralFixed = 0x18000000, 874 LoadLiteralFMask = 0x3B000000, 875 LoadLiteralMask = 0xFF000000, 876 LDR_w_lit = LoadLiteralFixed | 0x00000000, 877 LDR_x_lit = LoadLiteralFixed | 0x40000000, 878 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 879 PRFM_lit = LoadLiteralFixed | 0xC0000000, 880 LDR_s_lit = LoadLiteralFixed | 0x04000000, 881 LDR_d_lit = LoadLiteralFixed | 0x44000000, 882 LDR_q_lit = LoadLiteralFixed | 0x84000000 883 }; 884 885 #define LOAD_STORE_OP_LIST(V) \ 886 V(ST, RB, w, 0x00000000), \ 887 V(ST, RH, w, 0x40000000), \ 888 V(ST, R, w, 0x80000000), \ 889 V(ST, R, x, 0xC0000000), \ 890 V(LD, RB, w, 0x00400000), \ 891 V(LD, RH, w, 0x40400000), \ 892 V(LD, R, w, 0x80400000), \ 893 V(LD, R, x, 0xC0400000), \ 894 V(LD, RSB, x, 0x00800000), \ 895 V(LD, RSH, x, 0x40800000), \ 896 V(LD, RSW, x, 0x80800000), \ 897 V(LD, RSB, w, 0x00C00000), \ 898 V(LD, RSH, w, 0x40C00000), \ 899 V(ST, R, b, 0x04000000), \ 900 V(ST, R, h, 0x44000000), \ 901 V(ST, R, s, 0x84000000), \ 902 V(ST, R, d, 0xC4000000), \ 903 V(ST, R, q, 0x04800000), \ 904 V(LD, R, b, 0x04400000), \ 905 V(LD, R, h, 0x44400000), \ 906 V(LD, R, s, 0x84400000), \ 907 V(LD, R, d, 0xC4400000), \ 908 V(LD, R, q, 0x04C00000) 909 910 // Load/store (post, pre, offset and unsigned.) 911 enum LoadStoreOp { 912 LoadStoreMask = 0xC4C00000, 913 LoadStoreVMask = 0x04000000, 914 #define LOAD_STORE(A, B, C, D) \ 915 A##B##_##C = D 916 LOAD_STORE_OP_LIST(LOAD_STORE), 917 #undef LOAD_STORE 918 PRFM = 0xC0800000 919 }; 920 921 // Load/store unscaled offset. 922 enum LoadStoreUnscaledOffsetOp { 923 LoadStoreUnscaledOffsetFixed = 0x38000000, 924 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 925 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 926 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM, 927 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 928 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 929 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 930 #undef LOAD_STORE_UNSCALED 931 }; 932 933 // Load/store post index. 934 enum LoadStorePostIndex { 935 LoadStorePostIndexFixed = 0x38000400, 936 LoadStorePostIndexFMask = 0x3B200C00, 937 LoadStorePostIndexMask = 0xFFE00C00, 938 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 939 A##B##_##C##_post = LoadStorePostIndexFixed | D 940 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 941 #undef LOAD_STORE_POST_INDEX 942 }; 943 944 // Load/store pre index. 945 enum LoadStorePreIndex { 946 LoadStorePreIndexFixed = 0x38000C00, 947 LoadStorePreIndexFMask = 0x3B200C00, 948 LoadStorePreIndexMask = 0xFFE00C00, 949 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 950 A##B##_##C##_pre = LoadStorePreIndexFixed | D 951 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 952 #undef LOAD_STORE_PRE_INDEX 953 }; 954 955 // Load/store unsigned offset. 956 enum LoadStoreUnsignedOffset { 957 LoadStoreUnsignedOffsetFixed = 0x39000000, 958 LoadStoreUnsignedOffsetFMask = 0x3B000000, 959 LoadStoreUnsignedOffsetMask = 0xFFC00000, 960 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 961 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 962 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 963 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 964 #undef LOAD_STORE_UNSIGNED_OFFSET 965 }; 966 967 // Load/store register offset. 968 enum LoadStoreRegisterOffset { 969 LoadStoreRegisterOffsetFixed = 0x38200800, 970 LoadStoreRegisterOffsetFMask = 0x3B200C00, 971 LoadStoreRegisterOffsetMask = 0xFFE00C00, 972 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 973 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 974 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 975 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 976 #undef LOAD_STORE_REGISTER_OFFSET 977 }; 978 979 enum LoadStoreExclusive { 980 LoadStoreExclusiveFixed = 0x08000000, 981 LoadStoreExclusiveFMask = 0x3F000000, 982 LoadStoreExclusiveMask = 0xFFE08000, 983 STXRB_w = LoadStoreExclusiveFixed | 0x00000000, 984 STXRH_w = LoadStoreExclusiveFixed | 0x40000000, 985 STXR_w = LoadStoreExclusiveFixed | 0x80000000, 986 STXR_x = LoadStoreExclusiveFixed | 0xC0000000, 987 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000, 988 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000, 989 LDXR_w = LoadStoreExclusiveFixed | 0x80400000, 990 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000, 991 STXP_w = LoadStoreExclusiveFixed | 0x80200000, 992 STXP_x = LoadStoreExclusiveFixed | 0xC0200000, 993 LDXP_w = LoadStoreExclusiveFixed | 0x80600000, 994 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000, 995 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000, 996 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000, 997 STLXR_w = LoadStoreExclusiveFixed | 0x80008000, 998 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000, 999 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000, 1000 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000, 1001 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000, 1002 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000, 1003 STLXP_w = LoadStoreExclusiveFixed | 0x80208000, 1004 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000, 1005 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000, 1006 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000, 1007 STLRB_w = LoadStoreExclusiveFixed | 0x00808000, 1008 STLRH_w = LoadStoreExclusiveFixed | 0x40808000, 1009 STLR_w = LoadStoreExclusiveFixed | 0x80808000, 1010 STLR_x = LoadStoreExclusiveFixed | 0xC0808000, 1011 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000, 1012 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000, 1013 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000, 1014 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000, 1015 1016 // v8.1 Load/store LORegion ops 1017 STLLRB = LoadStoreExclusiveFixed | 0x00800000, 1018 LDLARB = LoadStoreExclusiveFixed | 0x00C00000, 1019 STLLRH = LoadStoreExclusiveFixed | 0x40800000, 1020 LDLARH = LoadStoreExclusiveFixed | 0x40C00000, 1021 STLLR_w = LoadStoreExclusiveFixed | 0x80800000, 1022 LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000, 1023 STLLR_x = LoadStoreExclusiveFixed | 0xC0800000, 1024 LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000, 1025 1026 // v8.1 Load/store exclusive ops 1027 LSEBit_l = 0x00400000, 1028 LSEBit_o0 = 0x00008000, 1029 LSEBit_sz = 0x40000000, 1030 CASFixed = LoadStoreExclusiveFixed | 0x80A00000, 1031 CASBFixed = LoadStoreExclusiveFixed | 0x00A00000, 1032 CASHFixed = LoadStoreExclusiveFixed | 0x40A00000, 1033 CASPFixed = LoadStoreExclusiveFixed | 0x00200000, 1034 CAS_w = CASFixed, 1035 CAS_x = CASFixed | LSEBit_sz, 1036 CASA_w = CASFixed | LSEBit_l, 1037 CASA_x = CASFixed | LSEBit_l | LSEBit_sz, 1038 CASL_w = CASFixed | LSEBit_o0, 1039 CASL_x = CASFixed | LSEBit_o0 | LSEBit_sz, 1040 CASAL_w = CASFixed | LSEBit_l | LSEBit_o0, 1041 CASAL_x = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz, 1042 CASB = CASBFixed, 1043 CASAB = CASBFixed | LSEBit_l, 1044 CASLB = CASBFixed | LSEBit_o0, 1045 CASALB = CASBFixed | LSEBit_l | LSEBit_o0, 1046 CASH = CASHFixed, 1047 CASAH = CASHFixed | LSEBit_l, 1048 CASLH = CASHFixed | LSEBit_o0, 1049 CASALH = CASHFixed | LSEBit_l | LSEBit_o0, 1050 CASP_w = CASPFixed, 1051 CASP_x = CASPFixed | LSEBit_sz, 1052 CASPA_w = CASPFixed | LSEBit_l, 1053 CASPA_x = CASPFixed | LSEBit_l | LSEBit_sz, 1054 CASPL_w = CASPFixed | LSEBit_o0, 1055 CASPL_x = CASPFixed | LSEBit_o0 | LSEBit_sz, 1056 CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0, 1057 CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz 1058 }; 1059 1060 #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \ 1061 V(LDADD, 0x00000000), \ 1062 V(LDCLR, 0x00001000), \ 1063 V(LDEOR, 0x00002000), \ 1064 V(LDSET, 0x00003000), \ 1065 V(LDSMAX, 0x00004000), \ 1066 V(LDSMIN, 0x00005000), \ 1067 V(LDUMAX, 0x00006000), \ 1068 V(LDUMIN, 0x00007000) 1069 1070 // Atomic memory. 1071 enum AtomicMemoryOp { 1072 AtomicMemoryFixed = 0x38200000, 1073 AtomicMemoryFMask = 0x3B200C00, 1074 AtomicMemoryMask = 0xFFE0FC00, 1075 SWPB = AtomicMemoryFixed | 0x00008000, 1076 SWPAB = AtomicMemoryFixed | 0x00808000, 1077 SWPLB = AtomicMemoryFixed | 0x00408000, 1078 SWPALB = AtomicMemoryFixed | 0x00C08000, 1079 SWPH = AtomicMemoryFixed | 0x40008000, 1080 SWPAH = AtomicMemoryFixed | 0x40808000, 1081 SWPLH = AtomicMemoryFixed | 0x40408000, 1082 SWPALH = AtomicMemoryFixed | 0x40C08000, 1083 SWP_w = AtomicMemoryFixed | 0x80008000, 1084 SWPA_w = AtomicMemoryFixed | 0x80808000, 1085 SWPL_w = AtomicMemoryFixed | 0x80408000, 1086 SWPAL_w = AtomicMemoryFixed | 0x80C08000, 1087 SWP_x = AtomicMemoryFixed | 0xC0008000, 1088 SWPA_x = AtomicMemoryFixed | 0xC0808000, 1089 SWPL_x = AtomicMemoryFixed | 0xC0408000, 1090 SWPAL_x = AtomicMemoryFixed | 0xC0C08000, 1091 LDAPRB = AtomicMemoryFixed | 0x0080C000, 1092 LDAPRH = AtomicMemoryFixed | 0x4080C000, 1093 LDAPR_w = AtomicMemoryFixed | 0x8080C000, 1094 LDAPR_x = AtomicMemoryFixed | 0xC080C000, 1095 1096 AtomicMemorySimpleFMask = 0x3B208C00, 1097 AtomicMemorySimpleOpMask = 0x00007000, 1098 #define ATOMIC_MEMORY_SIMPLE(N, OP) \ 1099 N##Op = OP, \ 1100 N##B = AtomicMemoryFixed | OP, \ 1101 N##AB = AtomicMemoryFixed | OP | 0x00800000, \ 1102 N##LB = AtomicMemoryFixed | OP | 0x00400000, \ 1103 N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \ 1104 N##H = AtomicMemoryFixed | OP | 0x40000000, \ 1105 N##AH = AtomicMemoryFixed | OP | 0x40800000, \ 1106 N##LH = AtomicMemoryFixed | OP | 0x40400000, \ 1107 N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \ 1108 N##_w = AtomicMemoryFixed | OP | 0x80000000, \ 1109 N##A_w = AtomicMemoryFixed | OP | 0x80800000, \ 1110 N##L_w = AtomicMemoryFixed | OP | 0x80400000, \ 1111 N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \ 1112 N##_x = AtomicMemoryFixed | OP | 0xC0000000, \ 1113 N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \ 1114 N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \ 1115 N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000 1116 1117 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE) 1118 #undef ATOMIC_MEMORY_SIMPLE 1119 }; 1120 1121 // Conditional compare. 1122 enum ConditionalCompareOp { 1123 ConditionalCompareMask = 0x60000000, 1124 CCMN = 0x20000000, 1125 CCMP = 0x60000000 1126 }; 1127 1128 // Conditional compare register. 1129 enum ConditionalCompareRegisterOp { 1130 ConditionalCompareRegisterFixed = 0x1A400000, 1131 ConditionalCompareRegisterFMask = 0x1FE00800, 1132 ConditionalCompareRegisterMask = 0xFFE00C10, 1133 CCMN_w = ConditionalCompareRegisterFixed | CCMN, 1134 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 1135 CCMP_w = ConditionalCompareRegisterFixed | CCMP, 1136 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 1137 }; 1138 1139 // Conditional compare immediate. 1140 enum ConditionalCompareImmediateOp { 1141 ConditionalCompareImmediateFixed = 0x1A400800, 1142 ConditionalCompareImmediateFMask = 0x1FE00800, 1143 ConditionalCompareImmediateMask = 0xFFE00C10, 1144 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 1145 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 1146 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 1147 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 1148 }; 1149 1150 // Conditional select. 1151 enum ConditionalSelectOp { 1152 ConditionalSelectFixed = 0x1A800000, 1153 ConditionalSelectFMask = 0x1FE00000, 1154 ConditionalSelectMask = 0xFFE00C00, 1155 CSEL_w = ConditionalSelectFixed | 0x00000000, 1156 CSEL_x = ConditionalSelectFixed | 0x80000000, 1157 CSEL = CSEL_w, 1158 CSINC_w = ConditionalSelectFixed | 0x00000400, 1159 CSINC_x = ConditionalSelectFixed | 0x80000400, 1160 CSINC = CSINC_w, 1161 CSINV_w = ConditionalSelectFixed | 0x40000000, 1162 CSINV_x = ConditionalSelectFixed | 0xC0000000, 1163 CSINV = CSINV_w, 1164 CSNEG_w = ConditionalSelectFixed | 0x40000400, 1165 CSNEG_x = ConditionalSelectFixed | 0xC0000400, 1166 CSNEG = CSNEG_w 1167 }; 1168 1169 // Data processing 1 source. 1170 enum DataProcessing1SourceOp { 1171 DataProcessing1SourceFixed = 0x5AC00000, 1172 DataProcessing1SourceFMask = 0x5FE00000, 1173 DataProcessing1SourceMask = 0xFFFFFC00, 1174 RBIT = DataProcessing1SourceFixed | 0x00000000, 1175 RBIT_w = RBIT, 1176 RBIT_x = RBIT | SixtyFourBits, 1177 REV16 = DataProcessing1SourceFixed | 0x00000400, 1178 REV16_w = REV16, 1179 REV16_x = REV16 | SixtyFourBits, 1180 REV = DataProcessing1SourceFixed | 0x00000800, 1181 REV_w = REV, 1182 REV32_x = REV | SixtyFourBits, 1183 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 1184 CLZ = DataProcessing1SourceFixed | 0x00001000, 1185 CLZ_w = CLZ, 1186 CLZ_x = CLZ | SixtyFourBits, 1187 CLS = DataProcessing1SourceFixed | 0x00001400, 1188 CLS_w = CLS, 1189 CLS_x = CLS | SixtyFourBits, 1190 1191 // Pointer authentication instructions in Armv8.3. 1192 PACIA = DataProcessing1SourceFixed | 0x80010000, 1193 PACIB = DataProcessing1SourceFixed | 0x80010400, 1194 PACDA = DataProcessing1SourceFixed | 0x80010800, 1195 PACDB = DataProcessing1SourceFixed | 0x80010C00, 1196 AUTIA = DataProcessing1SourceFixed | 0x80011000, 1197 AUTIB = DataProcessing1SourceFixed | 0x80011400, 1198 AUTDA = DataProcessing1SourceFixed | 0x80011800, 1199 AUTDB = DataProcessing1SourceFixed | 0x80011C00, 1200 PACIZA = DataProcessing1SourceFixed | 0x80012000, 1201 PACIZB = DataProcessing1SourceFixed | 0x80012400, 1202 PACDZA = DataProcessing1SourceFixed | 0x80012800, 1203 PACDZB = DataProcessing1SourceFixed | 0x80012C00, 1204 AUTIZA = DataProcessing1SourceFixed | 0x80013000, 1205 AUTIZB = DataProcessing1SourceFixed | 0x80013400, 1206 AUTDZA = DataProcessing1SourceFixed | 0x80013800, 1207 AUTDZB = DataProcessing1SourceFixed | 0x80013C00, 1208 XPACI = DataProcessing1SourceFixed | 0x80014000, 1209 XPACD = DataProcessing1SourceFixed | 0x80014400 1210 }; 1211 1212 // Data processing 2 source. 1213 enum DataProcessing2SourceOp { 1214 DataProcessing2SourceFixed = 0x1AC00000, 1215 DataProcessing2SourceFMask = 0x5FE00000, 1216 DataProcessing2SourceMask = 0xFFE0FC00, 1217 UDIV_w = DataProcessing2SourceFixed | 0x00000800, 1218 UDIV_x = DataProcessing2SourceFixed | 0x80000800, 1219 UDIV = UDIV_w, 1220 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 1221 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 1222 SDIV = SDIV_w, 1223 LSLV_w = DataProcessing2SourceFixed | 0x00002000, 1224 LSLV_x = DataProcessing2SourceFixed | 0x80002000, 1225 LSLV = LSLV_w, 1226 LSRV_w = DataProcessing2SourceFixed | 0x00002400, 1227 LSRV_x = DataProcessing2SourceFixed | 0x80002400, 1228 LSRV = LSRV_w, 1229 ASRV_w = DataProcessing2SourceFixed | 0x00002800, 1230 ASRV_x = DataProcessing2SourceFixed | 0x80002800, 1231 ASRV = ASRV_w, 1232 RORV_w = DataProcessing2SourceFixed | 0x00002C00, 1233 RORV_x = DataProcessing2SourceFixed | 0x80002C00, 1234 RORV = RORV_w, 1235 PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000, 1236 CRC32B = DataProcessing2SourceFixed | 0x00004000, 1237 CRC32H = DataProcessing2SourceFixed | 0x00004400, 1238 CRC32W = DataProcessing2SourceFixed | 0x00004800, 1239 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 1240 CRC32CB = DataProcessing2SourceFixed | 0x00005000, 1241 CRC32CH = DataProcessing2SourceFixed | 0x00005400, 1242 CRC32CW = DataProcessing2SourceFixed | 0x00005800, 1243 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 1244 }; 1245 1246 // Data processing 3 source. 1247 enum DataProcessing3SourceOp { 1248 DataProcessing3SourceFixed = 0x1B000000, 1249 DataProcessing3SourceFMask = 0x1F000000, 1250 DataProcessing3SourceMask = 0xFFE08000, 1251 MADD_w = DataProcessing3SourceFixed | 0x00000000, 1252 MADD_x = DataProcessing3SourceFixed | 0x80000000, 1253 MADD = MADD_w, 1254 MSUB_w = DataProcessing3SourceFixed | 0x00008000, 1255 MSUB_x = DataProcessing3SourceFixed | 0x80008000, 1256 MSUB = MSUB_w, 1257 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 1258 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 1259 SMULH_x = DataProcessing3SourceFixed | 0x80400000, 1260 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 1261 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 1262 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 1263 }; 1264 1265 // Floating point compare. 1266 enum FPCompareOp { 1267 FPCompareFixed = 0x1E202000, 1268 FPCompareFMask = 0x5F203C00, 1269 FPCompareMask = 0xFFE0FC1F, 1270 FCMP_h = FPCompareFixed | FP16 | 0x00000000, 1271 FCMP_s = FPCompareFixed | 0x00000000, 1272 FCMP_d = FPCompareFixed | FP64 | 0x00000000, 1273 FCMP = FCMP_s, 1274 FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008, 1275 FCMP_s_zero = FPCompareFixed | 0x00000008, 1276 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 1277 FCMP_zero = FCMP_s_zero, 1278 FCMPE_h = FPCompareFixed | FP16 | 0x00000010, 1279 FCMPE_s = FPCompareFixed | 0x00000010, 1280 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 1281 FCMPE = FCMPE_s, 1282 FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018, 1283 FCMPE_s_zero = FPCompareFixed | 0x00000018, 1284 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018, 1285 FCMPE_zero = FCMPE_s_zero 1286 }; 1287 1288 // Floating point conditional compare. 1289 enum FPConditionalCompareOp { 1290 FPConditionalCompareFixed = 0x1E200400, 1291 FPConditionalCompareFMask = 0x5F200C00, 1292 FPConditionalCompareMask = 0xFFE00C10, 1293 FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000, 1294 FCCMP_s = FPConditionalCompareFixed | 0x00000000, 1295 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 1296 FCCMP = FCCMP_s, 1297 FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010, 1298 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 1299 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 1300 FCCMPE = FCCMPE_s 1301 }; 1302 1303 // Floating point conditional select. 1304 enum FPConditionalSelectOp { 1305 FPConditionalSelectFixed = 0x1E200C00, 1306 FPConditionalSelectFMask = 0x5F200C00, 1307 FPConditionalSelectMask = 0xFFE00C00, 1308 FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000, 1309 FCSEL_s = FPConditionalSelectFixed | 0x00000000, 1310 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 1311 FCSEL = FCSEL_s 1312 }; 1313 1314 // Floating point immediate. 1315 enum FPImmediateOp { 1316 FPImmediateFixed = 0x1E201000, 1317 FPImmediateFMask = 0x5F201C00, 1318 FPImmediateMask = 0xFFE01C00, 1319 FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000, 1320 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1321 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1322 }; 1323 1324 // Floating point data processing 1 source. 1325 enum FPDataProcessing1SourceOp { 1326 FPDataProcessing1SourceFixed = 0x1E204000, 1327 FPDataProcessing1SourceFMask = 0x5F207C00, 1328 FPDataProcessing1SourceMask = 0xFFFFFC00, 1329 FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000, 1330 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1331 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1332 FMOV = FMOV_s, 1333 FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000, 1334 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1335 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1336 FABS = FABS_s, 1337 FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000, 1338 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1339 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1340 FNEG = FNEG_s, 1341 FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000, 1342 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1343 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1344 FSQRT = FSQRT_s, 1345 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1346 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1347 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000, 1348 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000, 1349 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000, 1350 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000, 1351 FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000, 1352 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1353 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1354 FRINTN = FRINTN_s, 1355 FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000, 1356 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1357 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1358 FRINTP = FRINTP_s, 1359 FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000, 1360 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1361 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1362 FRINTM = FRINTM_s, 1363 FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000, 1364 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1365 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1366 FRINTZ = FRINTZ_s, 1367 FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000, 1368 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1369 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1370 FRINTA = FRINTA_s, 1371 FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000, 1372 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1373 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1374 FRINTX = FRINTX_s, 1375 FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000, 1376 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1377 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1378 FRINTI = FRINTI_s 1379 }; 1380 1381 // Floating point data processing 2 source. 1382 enum FPDataProcessing2SourceOp { 1383 FPDataProcessing2SourceFixed = 0x1E200800, 1384 FPDataProcessing2SourceFMask = 0x5F200C00, 1385 FPDataProcessing2SourceMask = 0xFFE0FC00, 1386 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1387 FMUL_h = FMUL | FP16, 1388 FMUL_s = FMUL, 1389 FMUL_d = FMUL | FP64, 1390 FDIV = FPDataProcessing2SourceFixed | 0x00001000, 1391 FDIV_h = FDIV | FP16, 1392 FDIV_s = FDIV, 1393 FDIV_d = FDIV | FP64, 1394 FADD = FPDataProcessing2SourceFixed | 0x00002000, 1395 FADD_h = FADD | FP16, 1396 FADD_s = FADD, 1397 FADD_d = FADD | FP64, 1398 FSUB = FPDataProcessing2SourceFixed | 0x00003000, 1399 FSUB_h = FSUB | FP16, 1400 FSUB_s = FSUB, 1401 FSUB_d = FSUB | FP64, 1402 FMAX = FPDataProcessing2SourceFixed | 0x00004000, 1403 FMAX_h = FMAX | FP16, 1404 FMAX_s = FMAX, 1405 FMAX_d = FMAX | FP64, 1406 FMIN = FPDataProcessing2SourceFixed | 0x00005000, 1407 FMIN_h = FMIN | FP16, 1408 FMIN_s = FMIN, 1409 FMIN_d = FMIN | FP64, 1410 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 1411 FMAXNM_h = FMAXNM | FP16, 1412 FMAXNM_s = FMAXNM, 1413 FMAXNM_d = FMAXNM | FP64, 1414 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1415 FMINNM_h = FMINNM | FP16, 1416 FMINNM_s = FMINNM, 1417 FMINNM_d = FMINNM | FP64, 1418 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1419 FNMUL_h = FNMUL | FP16, 1420 FNMUL_s = FNMUL, 1421 FNMUL_d = FNMUL | FP64 1422 }; 1423 1424 // Floating point data processing 3 source. 1425 enum FPDataProcessing3SourceOp { 1426 FPDataProcessing3SourceFixed = 0x1F000000, 1427 FPDataProcessing3SourceFMask = 0x5F000000, 1428 FPDataProcessing3SourceMask = 0xFFE08000, 1429 FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000, 1430 FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000, 1431 FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000, 1432 FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000, 1433 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1434 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1435 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1436 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1437 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1438 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1439 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1440 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1441 }; 1442 1443 // Conversion between floating point and integer. 1444 enum FPIntegerConvertOp { 1445 FPIntegerConvertFixed = 0x1E200000, 1446 FPIntegerConvertFMask = 0x5F20FC00, 1447 FPIntegerConvertMask = 0xFFFFFC00, 1448 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1449 FCVTNS_wh = FCVTNS | FP16, 1450 FCVTNS_xh = FCVTNS | SixtyFourBits | FP16, 1451 FCVTNS_ws = FCVTNS, 1452 FCVTNS_xs = FCVTNS | SixtyFourBits, 1453 FCVTNS_wd = FCVTNS | FP64, 1454 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1455 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1456 FCVTNU_wh = FCVTNU | FP16, 1457 FCVTNU_xh = FCVTNU | SixtyFourBits | FP16, 1458 FCVTNU_ws = FCVTNU, 1459 FCVTNU_xs = FCVTNU | SixtyFourBits, 1460 FCVTNU_wd = FCVTNU | FP64, 1461 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1462 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1463 FCVTPS_wh = FCVTPS | FP16, 1464 FCVTPS_xh = FCVTPS | SixtyFourBits | FP16, 1465 FCVTPS_ws = FCVTPS, 1466 FCVTPS_xs = FCVTPS | SixtyFourBits, 1467 FCVTPS_wd = FCVTPS | FP64, 1468 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1469 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1470 FCVTPU_wh = FCVTPU | FP16, 1471 FCVTPU_xh = FCVTPU | SixtyFourBits | FP16, 1472 FCVTPU_ws = FCVTPU, 1473 FCVTPU_xs = FCVTPU | SixtyFourBits, 1474 FCVTPU_wd = FCVTPU | FP64, 1475 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1476 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1477 FCVTMS_wh = FCVTMS | FP16, 1478 FCVTMS_xh = FCVTMS | SixtyFourBits | FP16, 1479 FCVTMS_ws = FCVTMS, 1480 FCVTMS_xs = FCVTMS | SixtyFourBits, 1481 FCVTMS_wd = FCVTMS | FP64, 1482 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1483 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1484 FCVTMU_wh = FCVTMU | FP16, 1485 FCVTMU_xh = FCVTMU | SixtyFourBits | FP16, 1486 FCVTMU_ws = FCVTMU, 1487 FCVTMU_xs = FCVTMU | SixtyFourBits, 1488 FCVTMU_wd = FCVTMU | FP64, 1489 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1490 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1491 FCVTZS_wh = FCVTZS | FP16, 1492 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16, 1493 FCVTZS_ws = FCVTZS, 1494 FCVTZS_xs = FCVTZS | SixtyFourBits, 1495 FCVTZS_wd = FCVTZS | FP64, 1496 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1497 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1498 FCVTZU_wh = FCVTZU | FP16, 1499 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16, 1500 FCVTZU_ws = FCVTZU, 1501 FCVTZU_xs = FCVTZU | SixtyFourBits, 1502 FCVTZU_wd = FCVTZU | FP64, 1503 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1504 SCVTF = FPIntegerConvertFixed | 0x00020000, 1505 SCVTF_hw = SCVTF | FP16, 1506 SCVTF_hx = SCVTF | SixtyFourBits | FP16, 1507 SCVTF_sw = SCVTF, 1508 SCVTF_sx = SCVTF | SixtyFourBits, 1509 SCVTF_dw = SCVTF | FP64, 1510 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1511 UCVTF = FPIntegerConvertFixed | 0x00030000, 1512 UCVTF_hw = UCVTF | FP16, 1513 UCVTF_hx = UCVTF | SixtyFourBits | FP16, 1514 UCVTF_sw = UCVTF, 1515 UCVTF_sx = UCVTF | SixtyFourBits, 1516 UCVTF_dw = UCVTF | FP64, 1517 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1518 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1519 FCVTAS_wh = FCVTAS | FP16, 1520 FCVTAS_xh = FCVTAS | SixtyFourBits | FP16, 1521 FCVTAS_ws = FCVTAS, 1522 FCVTAS_xs = FCVTAS | SixtyFourBits, 1523 FCVTAS_wd = FCVTAS | FP64, 1524 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1525 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1526 FCVTAU_wh = FCVTAU | FP16, 1527 FCVTAU_xh = FCVTAU | SixtyFourBits | FP16, 1528 FCVTAU_ws = FCVTAU, 1529 FCVTAU_xs = FCVTAU | SixtyFourBits, 1530 FCVTAU_wd = FCVTAU | FP64, 1531 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1532 FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16, 1533 FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16, 1534 FMOV_xh = FMOV_wh | SixtyFourBits, 1535 FMOV_hx = FMOV_hw | SixtyFourBits, 1536 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1537 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1538 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1539 FMOV_dx = FMOV_sw | SixtyFourBits | FP64, 1540 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000, 1541 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000, 1542 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000 1543 }; 1544 1545 // Conversion between fixed point and floating point. 1546 enum FPFixedPointConvertOp { 1547 FPFixedPointConvertFixed = 0x1E000000, 1548 FPFixedPointConvertFMask = 0x5F200000, 1549 FPFixedPointConvertMask = 0xFFFF0000, 1550 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1551 FCVTZS_wh_fixed = FCVTZS_fixed | FP16, 1552 FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16, 1553 FCVTZS_ws_fixed = FCVTZS_fixed, 1554 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1555 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1556 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1557 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1558 FCVTZU_wh_fixed = FCVTZU_fixed | FP16, 1559 FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16, 1560 FCVTZU_ws_fixed = FCVTZU_fixed, 1561 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1562 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1563 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1564 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1565 SCVTF_hw_fixed = SCVTF_fixed | FP16, 1566 SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16, 1567 SCVTF_sw_fixed = SCVTF_fixed, 1568 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1569 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1570 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1571 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1572 UCVTF_hw_fixed = UCVTF_fixed | FP16, 1573 UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16, 1574 UCVTF_sw_fixed = UCVTF_fixed, 1575 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1576 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1577 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1578 }; 1579 1580 // Crypto - two register SHA. 1581 enum Crypto2RegSHAOp { 1582 Crypto2RegSHAFixed = 0x5E280800, 1583 Crypto2RegSHAFMask = 0xFF3E0C00 1584 }; 1585 1586 // Crypto - three register SHA. 1587 enum Crypto3RegSHAOp { 1588 Crypto3RegSHAFixed = 0x5E000000, 1589 Crypto3RegSHAFMask = 0xFF208C00 1590 }; 1591 1592 // Crypto - AES. 1593 enum CryptoAESOp { 1594 CryptoAESFixed = 0x4E280800, 1595 CryptoAESFMask = 0xFF3E0C00 1596 }; 1597 1598 // NEON instructions with two register operands. 1599 enum NEON2RegMiscOp { 1600 NEON2RegMiscFixed = 0x0E200800, 1601 NEON2RegMiscFMask = 0x9F3E0C00, 1602 NEON2RegMiscMask = 0xBF3FFC00, 1603 NEON2RegMiscUBit = 0x20000000, 1604 NEON_REV64 = NEON2RegMiscFixed | 0x00000000, 1605 NEON_REV32 = NEON2RegMiscFixed | 0x20000000, 1606 NEON_REV16 = NEON2RegMiscFixed | 0x00001000, 1607 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000, 1608 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit, 1609 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000, 1610 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit, 1611 NEON_CLS = NEON2RegMiscFixed | 0x00004000, 1612 NEON_CLZ = NEON2RegMiscFixed | 0x20004000, 1613 NEON_CNT = NEON2RegMiscFixed | 0x00005000, 1614 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000, 1615 NEON_SADALP = NEON2RegMiscFixed | 0x00006000, 1616 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit, 1617 NEON_SQABS = NEON2RegMiscFixed | 0x00007000, 1618 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000, 1619 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000, 1620 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000, 1621 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000, 1622 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000, 1623 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000, 1624 NEON_ABS = NEON2RegMiscFixed | 0x0000B000, 1625 NEON_NEG = NEON2RegMiscFixed | 0x2000B000, 1626 NEON_XTN = NEON2RegMiscFixed | 0x00012000, 1627 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000, 1628 NEON_SHLL = NEON2RegMiscFixed | 0x20013000, 1629 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000, 1630 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit, 1631 1632 NEON2RegMiscOpcode = 0x0001F000, 1633 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode, 1634 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode, 1635 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode, 1636 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode, 1637 1638 // These instructions use only one bit of the size field. The other bit is 1639 // used to distinguish between instructions. 1640 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000, 1641 NEON_FABS = NEON2RegMiscFixed | 0x0080F000, 1642 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000, 1643 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000, 1644 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000, 1645 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000, 1646 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000, 1647 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000, 1648 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000, 1649 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000, 1650 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000, 1651 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000, 1652 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000, 1653 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000, 1654 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit, 1655 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000, 1656 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit, 1657 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000, 1658 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit, 1659 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000, 1660 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit, 1661 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000, 1662 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit, 1663 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000, 1664 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000, 1665 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit, 1666 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000, 1667 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000, 1668 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000, 1669 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000, 1670 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000, 1671 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000, 1672 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000, 1673 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000, 1674 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000, 1675 1676 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode, 1677 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode 1678 }; 1679 1680 // NEON instructions with two register operands (FP16). 1681 enum NEON2RegMiscFP16Op { 1682 NEON2RegMiscFP16Fixed = 0x0E780800, 1683 NEON2RegMiscFP16FMask = 0x9F7E0C00, 1684 NEON2RegMiscFP16Mask = 0xBFFFFC00, 1685 NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000, 1686 NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000, 1687 NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000, 1688 NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000, 1689 NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000, 1690 NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000, 1691 NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000, 1692 NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000, 1693 NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000, 1694 NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000, 1695 NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000, 1696 NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000, 1697 NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000, 1698 NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000, 1699 NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000, 1700 NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000, 1701 NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000, 1702 NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000, 1703 NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000, 1704 NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000, 1705 NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000, 1706 NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000, 1707 NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000, 1708 NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000, 1709 NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000, 1710 NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000, 1711 NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000, 1712 NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000, 1713 NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000 1714 }; 1715 1716 // NEON instructions with three same-type operands. 1717 enum NEON3SameOp { 1718 NEON3SameFixed = 0x0E200400, 1719 NEON3SameFMask = 0x9F200400, 1720 NEON3SameMask = 0xBF20FC00, 1721 NEON3SameUBit = 0x20000000, 1722 NEON_ADD = NEON3SameFixed | 0x00008000, 1723 NEON_ADDP = NEON3SameFixed | 0x0000B800, 1724 NEON_SHADD = NEON3SameFixed | 0x00000000, 1725 NEON_SHSUB = NEON3SameFixed | 0x00002000, 1726 NEON_SRHADD = NEON3SameFixed | 0x00001000, 1727 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800, 1728 NEON_CMGE = NEON3SameFixed | 0x00003800, 1729 NEON_CMGT = NEON3SameFixed | 0x00003000, 1730 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT, 1731 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE, 1732 NEON_CMTST = NEON3SameFixed | 0x00008800, 1733 NEON_MLA = NEON3SameFixed | 0x00009000, 1734 NEON_MLS = NEON3SameFixed | 0x20009000, 1735 NEON_MUL = NEON3SameFixed | 0x00009800, 1736 NEON_PMUL = NEON3SameFixed | 0x20009800, 1737 NEON_SRSHL = NEON3SameFixed | 0x00005000, 1738 NEON_SQSHL = NEON3SameFixed | 0x00004800, 1739 NEON_SQRSHL = NEON3SameFixed | 0x00005800, 1740 NEON_SSHL = NEON3SameFixed | 0x00004000, 1741 NEON_SMAX = NEON3SameFixed | 0x00006000, 1742 NEON_SMAXP = NEON3SameFixed | 0x0000A000, 1743 NEON_SMIN = NEON3SameFixed | 0x00006800, 1744 NEON_SMINP = NEON3SameFixed | 0x0000A800, 1745 NEON_SABD = NEON3SameFixed | 0x00007000, 1746 NEON_SABA = NEON3SameFixed | 0x00007800, 1747 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD, 1748 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA, 1749 NEON_SQADD = NEON3SameFixed | 0x00000800, 1750 NEON_SQSUB = NEON3SameFixed | 0x00002800, 1751 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000, 1752 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD, 1753 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB, 1754 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD, 1755 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX, 1756 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP, 1757 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN, 1758 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP, 1759 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL, 1760 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD, 1761 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL, 1762 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL, 1763 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB, 1764 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL, 1765 NEON_SQDMULH = NEON3SameFixed | 0x0000B000, 1766 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000, 1767 1768 // NEON floating point instructions with three same-type operands. 1769 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000, 1770 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000, 1771 NEON3SameFPMask = NEON3SameMask | 0x00800000, 1772 NEON_FADD = NEON3SameFixed | 0x0000D000, 1773 NEON_FSUB = NEON3SameFixed | 0x0080D000, 1774 NEON_FMUL = NEON3SameFixed | 0x2000D800, 1775 NEON_FDIV = NEON3SameFixed | 0x2000F800, 1776 NEON_FMAX = NEON3SameFixed | 0x0000F000, 1777 NEON_FMAXNM = NEON3SameFixed | 0x0000C000, 1778 NEON_FMAXP = NEON3SameFixed | 0x2000F000, 1779 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000, 1780 NEON_FMIN = NEON3SameFixed | 0x0080F000, 1781 NEON_FMINNM = NEON3SameFixed | 0x0080C000, 1782 NEON_FMINP = NEON3SameFixed | 0x2080F000, 1783 NEON_FMINNMP = NEON3SameFixed | 0x2080C000, 1784 NEON_FMLA = NEON3SameFixed | 0x0000C800, 1785 NEON_FMLS = NEON3SameFixed | 0x0080C800, 1786 NEON_FMULX = NEON3SameFixed | 0x0000D800, 1787 NEON_FRECPS = NEON3SameFixed | 0x0000F800, 1788 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800, 1789 NEON_FABD = NEON3SameFixed | 0x2080D000, 1790 NEON_FADDP = NEON3SameFixed | 0x2000D000, 1791 NEON_FCMEQ = NEON3SameFixed | 0x0000E000, 1792 NEON_FCMGE = NEON3SameFixed | 0x2000E000, 1793 NEON_FCMGT = NEON3SameFixed | 0x2080E000, 1794 NEON_FACGE = NEON3SameFixed | 0x2000E800, 1795 NEON_FACGT = NEON3SameFixed | 0x2080E800, 1796 1797 // NEON logical instructions with three same-type operands. 1798 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800, 1799 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800, 1800 NEON3SameLogicalMask = 0xBFE0FC00, 1801 NEON3SameLogicalFormatMask = NEON_Q, 1802 NEON_AND = NEON3SameLogicalFixed | 0x00000000, 1803 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000, 1804 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000, 1805 NEON_EOR = NEON3SameLogicalFixed | 0x20000000, 1806 NEON_BIC = NEON3SameLogicalFixed | 0x00400000, 1807 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000, 1808 NEON_BIT = NEON3SameLogicalFixed | 0x20800000, 1809 NEON_BSL = NEON3SameLogicalFixed | 0x20400000 1810 }; 1811 1812 1813 enum NEON3SameFP16 { 1814 NEON3SameFP16Fixed = 0x0E400400, 1815 NEON3SameFP16FMask = 0x9F60C400, 1816 NEON3SameFP16Mask = 0xBFE0FC00, 1817 NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000, 1818 NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800, 1819 NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000, 1820 NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800, 1821 NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000, 1822 NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000, 1823 NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800, 1824 NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000, 1825 NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800, 1826 NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000, 1827 NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000, 1828 NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800, 1829 NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000, 1830 NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000, 1831 NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800, 1832 NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000, 1833 NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800, 1834 NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000, 1835 NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800, 1836 NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000, 1837 NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000, 1838 NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000, 1839 NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800, 1840 NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000 1841 }; 1842 1843 1844 // 'Extra' NEON instructions with three same-type operands. 1845 enum NEON3SameExtraOp { 1846 NEON3SameExtraFixed = 0x0E008400, 1847 NEON3SameExtraUBit = 0x20000000, 1848 NEON3SameExtraFMask = 0x9E208400, 1849 NEON3SameExtraMask = 0xBE20FC00, 1850 NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit, 1851 NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800, 1852 NEON_SDOT = NEON3SameExtraFixed | 0x00001000, 1853 NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000, 1854 1855 /* v8.3 Complex Numbers */ 1856 NEON3SameExtraFCFixed = 0x2E00C400, 1857 NEON3SameExtraFCFMask = 0xBF20C400, 1858 // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>. 1859 NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000, 1860 NEON_FCMLA = NEON3SameExtraFCFixed, 1861 // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>. 1862 NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800, 1863 NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000 1864 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED. 1865 }; 1866 1867 // NEON instructions with three different-type operands. 1868 enum NEON3DifferentOp { 1869 NEON3DifferentFixed = 0x0E200000, 1870 NEON3DifferentFMask = 0x9F200C00, 1871 NEON3DifferentMask = 0xFF20FC00, 1872 NEON_ADDHN = NEON3DifferentFixed | 0x00004000, 1873 NEON_ADDHN2 = NEON_ADDHN | NEON_Q, 1874 NEON_PMULL = NEON3DifferentFixed | 0x0000E000, 1875 NEON_PMULL2 = NEON_PMULL | NEON_Q, 1876 NEON_RADDHN = NEON3DifferentFixed | 0x20004000, 1877 NEON_RADDHN2 = NEON_RADDHN | NEON_Q, 1878 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000, 1879 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q, 1880 NEON_SABAL = NEON3DifferentFixed | 0x00005000, 1881 NEON_SABAL2 = NEON_SABAL | NEON_Q, 1882 NEON_SABDL = NEON3DifferentFixed | 0x00007000, 1883 NEON_SABDL2 = NEON_SABDL | NEON_Q, 1884 NEON_SADDL = NEON3DifferentFixed | 0x00000000, 1885 NEON_SADDL2 = NEON_SADDL | NEON_Q, 1886 NEON_SADDW = NEON3DifferentFixed | 0x00001000, 1887 NEON_SADDW2 = NEON_SADDW | NEON_Q, 1888 NEON_SMLAL = NEON3DifferentFixed | 0x00008000, 1889 NEON_SMLAL2 = NEON_SMLAL | NEON_Q, 1890 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000, 1891 NEON_SMLSL2 = NEON_SMLSL | NEON_Q, 1892 NEON_SMULL = NEON3DifferentFixed | 0x0000C000, 1893 NEON_SMULL2 = NEON_SMULL | NEON_Q, 1894 NEON_SSUBL = NEON3DifferentFixed | 0x00002000, 1895 NEON_SSUBL2 = NEON_SSUBL | NEON_Q, 1896 NEON_SSUBW = NEON3DifferentFixed | 0x00003000, 1897 NEON_SSUBW2 = NEON_SSUBW | NEON_Q, 1898 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000, 1899 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q, 1900 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000, 1901 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q, 1902 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000, 1903 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q, 1904 NEON_SUBHN = NEON3DifferentFixed | 0x00006000, 1905 NEON_SUBHN2 = NEON_SUBHN | NEON_Q, 1906 NEON_UABAL = NEON_SABAL | NEON3SameUBit, 1907 NEON_UABAL2 = NEON_UABAL | NEON_Q, 1908 NEON_UABDL = NEON_SABDL | NEON3SameUBit, 1909 NEON_UABDL2 = NEON_UABDL | NEON_Q, 1910 NEON_UADDL = NEON_SADDL | NEON3SameUBit, 1911 NEON_UADDL2 = NEON_UADDL | NEON_Q, 1912 NEON_UADDW = NEON_SADDW | NEON3SameUBit, 1913 NEON_UADDW2 = NEON_UADDW | NEON_Q, 1914 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit, 1915 NEON_UMLAL2 = NEON_UMLAL | NEON_Q, 1916 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit, 1917 NEON_UMLSL2 = NEON_UMLSL | NEON_Q, 1918 NEON_UMULL = NEON_SMULL | NEON3SameUBit, 1919 NEON_UMULL2 = NEON_UMULL | NEON_Q, 1920 NEON_USUBL = NEON_SSUBL | NEON3SameUBit, 1921 NEON_USUBL2 = NEON_USUBL | NEON_Q, 1922 NEON_USUBW = NEON_SSUBW | NEON3SameUBit, 1923 NEON_USUBW2 = NEON_USUBW | NEON_Q 1924 }; 1925 1926 // NEON instructions operating across vectors. 1927 enum NEONAcrossLanesOp { 1928 NEONAcrossLanesFixed = 0x0E300800, 1929 NEONAcrossLanesFMask = 0x9F3E0C00, 1930 NEONAcrossLanesMask = 0xBF3FFC00, 1931 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000, 1932 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000, 1933 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000, 1934 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000, 1935 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000, 1936 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000, 1937 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000, 1938 1939 NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000, 1940 NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000, 1941 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000, 1942 NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000, 1943 NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000, 1944 NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000, 1945 NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000, 1946 1947 // NEON floating point across instructions. 1948 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000, 1949 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000, 1950 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000, 1951 1952 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000, 1953 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000, 1954 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000, 1955 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000 1956 }; 1957 1958 // NEON instructions with indexed element operand. 1959 enum NEONByIndexedElementOp { 1960 NEONByIndexedElementFixed = 0x0F000000, 1961 NEONByIndexedElementFMask = 0x9F000400, 1962 NEONByIndexedElementMask = 0xBF00F400, 1963 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000, 1964 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000, 1965 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000, 1966 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000, 1967 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000, 1968 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000, 1969 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000, 1970 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000, 1971 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000, 1972 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000, 1973 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000, 1974 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000, 1975 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000, 1976 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000, 1977 NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000, 1978 NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000, 1979 NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000, 1980 NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000, 1981 NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000, 1982 NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000, 1983 NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000, 1984 NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000, 1985 1986 // Floating point instructions. 1987 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000, 1988 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000, 1989 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000, 1990 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000, 1991 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000, 1992 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000, 1993 NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000, 1994 1995 // Complex instruction(s) this is necessary because 'rot' encoding moves into the NEONByIndex..Mask space 1996 NEONByIndexedElementFPComplexMask = 0xBF009400 1997 }; 1998 1999 // NEON register copy. 2000 enum NEONCopyOp { 2001 NEONCopyFixed = 0x0E000400, 2002 NEONCopyFMask = 0x9FE08400, 2003 NEONCopyMask = 0x3FE08400, 2004 NEONCopyInsElementMask = NEONCopyMask | 0x40000000, 2005 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800, 2006 NEONCopyDupElementMask = NEONCopyMask | 0x20007800, 2007 NEONCopyDupGeneralMask = NEONCopyDupElementMask, 2008 NEONCopyUmovMask = NEONCopyMask | 0x20007800, 2009 NEONCopySmovMask = NEONCopyMask | 0x20007800, 2010 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000, 2011 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800, 2012 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000, 2013 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800, 2014 NEON_SMOV = NEONCopyFixed | 0x00002800, 2015 NEON_UMOV = NEONCopyFixed | 0x00003800 2016 }; 2017 2018 // NEON extract. 2019 enum NEONExtractOp { 2020 NEONExtractFixed = 0x2E000000, 2021 NEONExtractFMask = 0xBF208400, 2022 NEONExtractMask = 0xBFE08400, 2023 NEON_EXT = NEONExtractFixed | 0x00000000 2024 }; 2025 2026 enum NEONLoadStoreMultiOp { 2027 NEONLoadStoreMultiL = 0x00400000, 2028 NEONLoadStoreMulti1_1v = 0x00007000, 2029 NEONLoadStoreMulti1_2v = 0x0000A000, 2030 NEONLoadStoreMulti1_3v = 0x00006000, 2031 NEONLoadStoreMulti1_4v = 0x00002000, 2032 NEONLoadStoreMulti2 = 0x00008000, 2033 NEONLoadStoreMulti3 = 0x00004000, 2034 NEONLoadStoreMulti4 = 0x00000000 2035 }; 2036 2037 // NEON load/store multiple structures. 2038 enum NEONLoadStoreMultiStructOp { 2039 NEONLoadStoreMultiStructFixed = 0x0C000000, 2040 NEONLoadStoreMultiStructFMask = 0xBFBF0000, 2041 NEONLoadStoreMultiStructMask = 0xBFFFF000, 2042 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed, 2043 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed | 2044 NEONLoadStoreMultiL, 2045 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v, 2046 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v, 2047 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v, 2048 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v, 2049 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2, 2050 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3, 2051 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4, 2052 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v, 2053 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v, 2054 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v, 2055 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v, 2056 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2, 2057 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3, 2058 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4 2059 }; 2060 2061 // NEON load/store multiple structures with post-index addressing. 2062 enum NEONLoadStoreMultiStructPostIndexOp { 2063 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000, 2064 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000, 2065 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000, 2066 NEONLoadStoreMultiStructPostIndex = 0x00800000, 2067 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex, 2068 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex, 2069 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex, 2070 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex, 2071 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex, 2072 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex, 2073 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex, 2074 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex, 2075 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex, 2076 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex, 2077 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex, 2078 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex, 2079 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex, 2080 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex 2081 }; 2082 2083 enum NEONLoadStoreSingleOp { 2084 NEONLoadStoreSingle1 = 0x00000000, 2085 NEONLoadStoreSingle2 = 0x00200000, 2086 NEONLoadStoreSingle3 = 0x00002000, 2087 NEONLoadStoreSingle4 = 0x00202000, 2088 NEONLoadStoreSingleL = 0x00400000, 2089 NEONLoadStoreSingle_b = 0x00000000, 2090 NEONLoadStoreSingle_h = 0x00004000, 2091 NEONLoadStoreSingle_s = 0x00008000, 2092 NEONLoadStoreSingle_d = 0x00008400, 2093 NEONLoadStoreSingleAllLanes = 0x0000C000, 2094 NEONLoadStoreSingleLenMask = 0x00202000 2095 }; 2096 2097 // NEON load/store single structure. 2098 enum NEONLoadStoreSingleStructOp { 2099 NEONLoadStoreSingleStructFixed = 0x0D000000, 2100 NEONLoadStoreSingleStructFMask = 0xBF9F0000, 2101 NEONLoadStoreSingleStructMask = 0xBFFFE000, 2102 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed, 2103 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | 2104 NEONLoadStoreSingleL, 2105 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 | 2106 NEONLoadStoreSingleStructLoad, 2107 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 | 2108 NEONLoadStoreSingleStructLoad, 2109 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 | 2110 NEONLoadStoreSingleStructLoad, 2111 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 | 2112 NEONLoadStoreSingleStructLoad, 2113 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 | 2114 NEONLoadStoreSingleStructFixed, 2115 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 | 2116 NEONLoadStoreSingleStructFixed, 2117 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 | 2118 NEONLoadStoreSingleStructFixed, 2119 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 | 2120 NEONLoadStoreSingleStructFixed, 2121 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b, 2122 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h, 2123 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s, 2124 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d, 2125 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes, 2126 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b, 2127 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h, 2128 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s, 2129 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d, 2130 2131 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b, 2132 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h, 2133 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s, 2134 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d, 2135 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes, 2136 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b, 2137 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h, 2138 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s, 2139 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d, 2140 2141 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b, 2142 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h, 2143 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s, 2144 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d, 2145 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes, 2146 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b, 2147 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h, 2148 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s, 2149 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d, 2150 2151 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b, 2152 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h, 2153 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s, 2154 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d, 2155 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes, 2156 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b, 2157 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h, 2158 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s, 2159 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d 2160 }; 2161 2162 // NEON load/store single structure with post-index addressing. 2163 enum NEONLoadStoreSingleStructPostIndexOp { 2164 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000, 2165 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000, 2166 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000, 2167 NEONLoadStoreSingleStructPostIndex = 0x00800000, 2168 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex, 2169 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex, 2170 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex, 2171 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex, 2172 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex, 2173 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex, 2174 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex, 2175 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex, 2176 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex, 2177 2178 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex, 2179 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex, 2180 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex, 2181 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex, 2182 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex, 2183 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex, 2184 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex, 2185 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex, 2186 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex, 2187 2188 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex, 2189 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex, 2190 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex, 2191 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex, 2192 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex, 2193 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex, 2194 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex, 2195 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex, 2196 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex, 2197 2198 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex, 2199 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex, 2200 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex, 2201 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex, 2202 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex, 2203 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex, 2204 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex, 2205 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex, 2206 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex 2207 }; 2208 2209 // NEON modified immediate. 2210 enum NEONModifiedImmediateOp { 2211 NEONModifiedImmediateFixed = 0x0F000400, 2212 NEONModifiedImmediateFMask = 0x9FF80400, 2213 NEONModifiedImmediateOpBit = 0x20000000, 2214 NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800, 2215 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000, 2216 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000, 2217 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000, 2218 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000 2219 }; 2220 2221 // NEON shift immediate. 2222 enum NEONShiftImmediateOp { 2223 NEONShiftImmediateFixed = 0x0F000400, 2224 NEONShiftImmediateFMask = 0x9F800400, 2225 NEONShiftImmediateMask = 0xBF80FC00, 2226 NEONShiftImmediateUBit = 0x20000000, 2227 NEON_SHL = NEONShiftImmediateFixed | 0x00005000, 2228 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000, 2229 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000, 2230 NEON_SLI = NEONShiftImmediateFixed | 0x20005000, 2231 NEON_SRI = NEONShiftImmediateFixed | 0x20004000, 2232 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000, 2233 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800, 2234 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000, 2235 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800, 2236 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000, 2237 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800, 2238 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000, 2239 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800, 2240 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000, 2241 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000, 2242 NEON_USHR = NEONShiftImmediateFixed | 0x20000000, 2243 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000, 2244 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000, 2245 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000, 2246 NEON_USRA = NEONShiftImmediateFixed | 0x20001000, 2247 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000, 2248 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000, 2249 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000, 2250 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000, 2251 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800, 2252 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800, 2253 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000, 2254 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000 2255 }; 2256 2257 // NEON table. 2258 enum NEONTableOp { 2259 NEONTableFixed = 0x0E000000, 2260 NEONTableFMask = 0xBF208C00, 2261 NEONTableExt = 0x00001000, 2262 NEONTableMask = 0xBF20FC00, 2263 NEON_TBL_1v = NEONTableFixed | 0x00000000, 2264 NEON_TBL_2v = NEONTableFixed | 0x00002000, 2265 NEON_TBL_3v = NEONTableFixed | 0x00004000, 2266 NEON_TBL_4v = NEONTableFixed | 0x00006000, 2267 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt, 2268 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt, 2269 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt, 2270 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt 2271 }; 2272 2273 // NEON perm. 2274 enum NEONPermOp { 2275 NEONPermFixed = 0x0E000800, 2276 NEONPermFMask = 0xBF208C00, 2277 NEONPermMask = 0x3F20FC00, 2278 NEON_UZP1 = NEONPermFixed | 0x00001000, 2279 NEON_TRN1 = NEONPermFixed | 0x00002000, 2280 NEON_ZIP1 = NEONPermFixed | 0x00003000, 2281 NEON_UZP2 = NEONPermFixed | 0x00005000, 2282 NEON_TRN2 = NEONPermFixed | 0x00006000, 2283 NEON_ZIP2 = NEONPermFixed | 0x00007000 2284 }; 2285 2286 // NEON scalar instructions with two register operands. 2287 enum NEONScalar2RegMiscOp { 2288 NEONScalar2RegMiscFixed = 0x5E200800, 2289 NEONScalar2RegMiscFMask = 0xDF3E0C00, 2290 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask, 2291 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero, 2292 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero, 2293 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero, 2294 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero, 2295 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero, 2296 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS, 2297 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS, 2298 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG, 2299 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG, 2300 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN, 2301 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN, 2302 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN, 2303 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD, 2304 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD, 2305 2306 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode, 2307 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode, 2308 2309 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000, 2310 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE, 2311 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE, 2312 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF, 2313 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF, 2314 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero, 2315 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero, 2316 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero, 2317 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero, 2318 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero, 2319 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000, 2320 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS, 2321 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU, 2322 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS, 2323 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU, 2324 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS, 2325 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU, 2326 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS, 2327 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU, 2328 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS, 2329 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU, 2330 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN 2331 }; 2332 2333 // NEON instructions with two register operands (FP16). 2334 enum NEONScalar2RegMiscFP16Op { 2335 NEONScalar2RegMiscFP16Fixed = 0x5E780800, 2336 NEONScalar2RegMiscFP16FMask = 0xDF7E0C00, 2337 NEONScalar2RegMiscFP16Mask = 0xFFFFFC00, 2338 NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H, 2339 NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H, 2340 NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H, 2341 NEON_SCVTF_H_scalar = NEON_Q | NEONScalar | NEON_SCVTF_H, 2342 NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero, 2343 NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero, 2344 NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero, 2345 NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H, 2346 NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H, 2347 NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H, 2348 NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000, 2349 NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H, 2350 NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H, 2351 NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H, 2352 NEON_UCVTF_H_scalar = NEON_Q | NEONScalar | NEON_UCVTF_H, 2353 NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero, 2354 NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero, 2355 NEON_FCVTPU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPU_H, 2356 NEON_FCVTZU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_H, 2357 NEON_FRSQRTE_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE_H 2358 }; 2359 2360 // NEON scalar instructions with three same-type operands. 2361 enum NEONScalar3SameOp { 2362 NEONScalar3SameFixed = 0x5E200400, 2363 NEONScalar3SameFMask = 0xDF200400, 2364 NEONScalar3SameMask = 0xFF20FC00, 2365 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD, 2366 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ, 2367 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE, 2368 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT, 2369 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI, 2370 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS, 2371 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST, 2372 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB, 2373 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD, 2374 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD, 2375 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB, 2376 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB, 2377 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL, 2378 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL, 2379 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL, 2380 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL, 2381 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL, 2382 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL, 2383 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL, 2384 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL, 2385 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH, 2386 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH, 2387 2388 // NEON floating point scalar instructions with three same-type operands. 2389 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000, 2390 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000, 2391 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000, 2392 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE, 2393 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT, 2394 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ, 2395 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE, 2396 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT, 2397 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX, 2398 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS, 2399 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS, 2400 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD 2401 }; 2402 2403 // NEON scalar FP16 instructions with three same-type operands. 2404 enum NEONScalar3SameFP16Op { 2405 NEONScalar3SameFP16Fixed = 0x5E400400, 2406 NEONScalar3SameFP16FMask = 0xDF60C400, 2407 NEONScalar3SameFP16Mask = 0xFFE0FC00, 2408 NEON_FABD_H_scalar = NEON_Q | NEONScalar | NEON_FABD_H, 2409 NEON_FMULX_H_scalar = NEON_Q | NEONScalar | NEON_FMULX_H, 2410 NEON_FCMEQ_H_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H, 2411 NEON_FCMGE_H_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H, 2412 NEON_FCMGT_H_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H, 2413 NEON_FACGE_H_scalar = NEON_Q | NEONScalar | NEON_FACGE_H, 2414 NEON_FACGT_H_scalar = NEON_Q | NEONScalar | NEON_FACGT_H, 2415 NEON_FRECPS_H_scalar = NEON_Q | NEONScalar | NEON_FRECPS_H, 2416 NEON_FRSQRTS_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS_H 2417 }; 2418 2419 // 'Extra' NEON scalar instructions with three same-type operands. 2420 enum NEONScalar3SameExtraOp { 2421 NEONScalar3SameExtraFixed = 0x5E008400, 2422 NEONScalar3SameExtraFMask = 0xDF208400, 2423 NEONScalar3SameExtraMask = 0xFF20FC00, 2424 NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH, 2425 NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH 2426 }; 2427 2428 // NEON scalar instructions with three different-type operands. 2429 enum NEONScalar3DiffOp { 2430 NEONScalar3DiffFixed = 0x5E200000, 2431 NEONScalar3DiffFMask = 0xDF200C00, 2432 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask, 2433 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL, 2434 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL, 2435 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL 2436 }; 2437 2438 // NEON scalar instructions with indexed element operand. 2439 enum NEONScalarByIndexedElementOp { 2440 NEONScalarByIndexedElementFixed = 0x5F000000, 2441 NEONScalarByIndexedElementFMask = 0xDF000400, 2442 NEONScalarByIndexedElementMask = 0xFF00F400, 2443 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement, 2444 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement, 2445 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement, 2446 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement, 2447 NEON_SQRDMULH_byelement_scalar 2448 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement, 2449 NEON_SQRDMLAH_byelement_scalar 2450 = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement, 2451 NEON_SQRDMLSH_byelement_scalar 2452 = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement, 2453 NEON_FMLA_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_H_byelement, 2454 NEON_FMLS_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_H_byelement, 2455 NEON_FMUL_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_H_byelement, 2456 NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement, 2457 2458 // Floating point instructions. 2459 NEONScalarByIndexedElementFPFixed 2460 = NEONScalarByIndexedElementFixed | 0x00800000, 2461 NEONScalarByIndexedElementFPMask 2462 = NEONScalarByIndexedElementMask | 0x00800000, 2463 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement, 2464 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement, 2465 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement, 2466 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement 2467 }; 2468 2469 // NEON scalar register copy. 2470 enum NEONScalarCopyOp { 2471 NEONScalarCopyFixed = 0x5E000400, 2472 NEONScalarCopyFMask = 0xDFE08400, 2473 NEONScalarCopyMask = 0xFFE0FC00, 2474 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT 2475 }; 2476 2477 // NEON scalar pairwise instructions. 2478 enum NEONScalarPairwiseOp { 2479 NEONScalarPairwiseFixed = 0x5E300800, 2480 NEONScalarPairwiseFMask = 0xDF3E0C00, 2481 NEONScalarPairwiseMask = 0xFFB1F800, 2482 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000, 2483 NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000, 2484 NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000, 2485 NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000, 2486 NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000, 2487 NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000, 2488 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000, 2489 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000, 2490 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000, 2491 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000, 2492 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000 2493 }; 2494 2495 // NEON scalar shift immediate. 2496 enum NEONScalarShiftImmediateOp { 2497 NEONScalarShiftImmediateFixed = 0x5F000400, 2498 NEONScalarShiftImmediateFMask = 0xDF800400, 2499 NEONScalarShiftImmediateMask = 0xFF80FC00, 2500 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL, 2501 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI, 2502 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI, 2503 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR, 2504 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR, 2505 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR, 2506 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR, 2507 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA, 2508 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA, 2509 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA, 2510 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA, 2511 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN, 2512 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN, 2513 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN, 2514 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN, 2515 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN, 2516 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN, 2517 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU, 2518 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm, 2519 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm, 2520 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm, 2521 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm, 2522 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm, 2523 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm 2524 }; 2525 2526 // Unimplemented and unallocated instructions. These are defined to make fixed 2527 // bit assertion easier. 2528 enum UnimplementedOp { 2529 UnimplementedFixed = 0x00000000, 2530 UnimplementedFMask = 0x00000000 2531 }; 2532 2533 enum UnallocatedOp { 2534 UnallocatedFixed = 0x00000000, 2535 UnallocatedFMask = 0x00000000 2536 }; 2537 2538 // Re-enable `clang-format` after the `enum`s. 2539 // clang-format on 2540 2541 } // namespace aarch64 2542 } // namespace vixl 2543 2544 #endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_ 2545
