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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * (C) Copyright 2009 Faraday Technology
      4  * Po-Yu Chuang <ratbert (at) faraday-tech.com>
      5  */
      6 
      7 /*
      8  * Static Memory Controller
      9  */
     10 #ifndef __FTSMC020_H
     11 #define __FTSMC020_H
     12 
     13 #ifndef __ASSEMBLY__
     14 
     15 struct ftsmc020_bank {
     16 	unsigned int    cr;
     17 	unsigned int    tpr;
     18 };
     19 
     20 struct ftsmc020 {
     21 	struct ftsmc020_bank bank[4];	/* 0x00 - 0x1c */
     22 	unsigned int	pad[8];		/* 0x20 - 0x3c */
     23 	unsigned int	ssr;		/* 0x40 */
     24 };
     25 
     26 void ftsmc020_init(void);
     27 
     28 #endif /* __ASSEMBLY__ */
     29 
     30 /*
     31  * Memory Bank Configuration Register
     32  */
     33 #define FTSMC020_BANK_ENABLE	(1 << 28)
     34 #define FTSMC020_BANK_BASE(x)	((x) & 0x0fff1000)
     35 
     36 #define FTSMC020_BANK_WPROT	(1 << 11)
     37 
     38 #define FTSMC020_BANK_TYPE1	(1 << 10)
     39 #define FTSMC020_BANK_TYPE2	(1 << 9)
     40 #define FTSMC020_BANK_TYPE3	(1 << 8)
     41 
     42 #define FTSMC020_BANK_SIZE_32K	(0xb << 4)
     43 #define FTSMC020_BANK_SIZE_64K	(0xc << 4)
     44 #define FTSMC020_BANK_SIZE_128K	(0xd << 4)
     45 #define FTSMC020_BANK_SIZE_256K	(0xe << 4)
     46 #define FTSMC020_BANK_SIZE_512K	(0xf << 4)
     47 #define FTSMC020_BANK_SIZE_1M	(0x0 << 4)
     48 #define FTSMC020_BANK_SIZE_2M	(0x1 << 4)
     49 #define FTSMC020_BANK_SIZE_4M	(0x2 << 4)
     50 #define FTSMC020_BANK_SIZE_8M	(0x3 << 4)
     51 #define FTSMC020_BANK_SIZE_16M	(0x4 << 4)
     52 #define FTSMC020_BANK_SIZE_32M	(0x5 << 4)
     53 #define FTSMC020_BANK_SIZE_64M	(0x6 << 4)
     54 
     55 #define FTSMC020_BANK_MBW_8	(0x0 << 0)
     56 #define FTSMC020_BANK_MBW_16	(0x1 << 0)
     57 #define FTSMC020_BANK_MBW_32	(0x2 << 0)
     58 
     59 /*
     60  * Memory Bank Timing Parameter Register
     61  */
     62 #define FTSMC020_TPR_ETRNA(x)	(((x) & 0xf) << 28)
     63 #define FTSMC020_TPR_EATI(x)	(((x) & 0xf) << 24)
     64 #define FTSMC020_TPR_RBE	(1 << 20)
     65 #define FTSMC020_TPR_AST(x)	(((x) & 0x3) << 18)
     66 #define FTSMC020_TPR_CTW(x)	(((x) & 0x3) << 16)
     67 #define FTSMC020_TPR_ATI(x)	(((x) & 0xf) << 12)
     68 #define FTSMC020_TPR_AT2(x)	(((x) & 0x3) << 8)
     69 #define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
     70 #define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
     71 #define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
     72 
     73 #endif	/* __FTSMC020_H */
     74