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    Searched defs:FalseReg (Results 1 - 6 of 6) sorted by null

  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 640 auto FalseReg = MIB->getOperand(3).getReg();
642 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
647 .addUse(FalseReg)
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 244 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
249 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
291 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg)
298 .addReg(FalseReg)
    [all...]
WebAssemblyFastISel.cpp 865 unsigned FalseReg = getRegForValue(Select->getFalseValue());
866 if (FalseReg == 0)
870 std::swap(TrueReg, FalseReg);
905 .addReg(FalseReg)
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86CmovConversion.cpp 721 unsigned FalseReg =
726 auto FRIt = FalseBBRegRewriteTable.find(FalseReg);
729 FalseReg = FRIt->second;
731 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
    [all...]
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 728 unsigned FalseReg = getRegForValue(Select->getFalseValue());
729 if (FalseReg == 0)
733 std::swap(TrueReg, FalseReg);
764 .addReg(FalseReg)
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp     [all...]

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