1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_ 18 #define ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_ 19 20 #include "constants_mips64.h" 21 #include "utils/managed_register.h" 22 23 namespace art { 24 namespace mips64 { 25 26 const int kNumberOfGpuRegIds = kNumberOfGpuRegisters; 27 const int kNumberOfGpuAllocIds = kNumberOfGpuRegisters; 28 29 const int kNumberOfFpuRegIds = kNumberOfFpuRegisters; 30 const int kNumberOfFpuAllocIds = kNumberOfFpuRegisters; 31 32 const int kNumberOfVecRegIds = kNumberOfVectorRegisters; 33 const int kNumberOfVecAllocIds = kNumberOfVectorRegisters; 34 35 const int kNumberOfRegIds = kNumberOfGpuRegIds + kNumberOfFpuRegIds + kNumberOfVecRegIds; 36 const int kNumberOfAllocIds = kNumberOfGpuAllocIds + kNumberOfFpuAllocIds + kNumberOfVecAllocIds; 37 38 // Register ids map: 39 // [0..R[ core registers (enum GpuRegister) 40 // [R..F[ floating-point registers (enum FpuRegister) 41 // [F..W[ MSA vector registers (enum VectorRegister) 42 // where 43 // R = kNumberOfGpuRegIds 44 // F = R + kNumberOfFpuRegIds 45 // W = F + kNumberOfVecRegIds 46 47 // An instance of class 'ManagedRegister' represents a single Mips64 register. 48 // A register can be one of the following: 49 // * core register (enum GpuRegister) 50 // * floating-point register (enum FpuRegister) 51 // * MSA vector register (enum VectorRegister) 52 // 53 // 'ManagedRegister::NoRegister()' provides an invalid register. 54 // There is a one-to-one mapping between ManagedRegister and register id. 55 class Mips64ManagedRegister : public ManagedRegister { 56 public: 57 constexpr GpuRegister AsGpuRegister() const { 58 CHECK(IsGpuRegister()); 59 return static_cast<GpuRegister>(id_); 60 } 61 62 constexpr FpuRegister AsFpuRegister() const { 63 CHECK(IsFpuRegister()); 64 return static_cast<FpuRegister>(id_ - kNumberOfGpuRegIds); 65 } 66 67 constexpr VectorRegister AsVectorRegister() const { 68 CHECK(IsVectorRegister()); 69 return static_cast<VectorRegister>(id_ - (kNumberOfGpuRegIds + kNumberOfFpuRegisters)); 70 } 71 72 constexpr FpuRegister AsOverlappingFpuRegister() const { 73 CHECK(IsValidManagedRegister()); 74 return static_cast<FpuRegister>(AsVectorRegister()); 75 } 76 77 constexpr VectorRegister AsOverlappingVectorRegister() const { 78 CHECK(IsValidManagedRegister()); 79 return static_cast<VectorRegister>(AsFpuRegister()); 80 } 81 82 constexpr bool IsGpuRegister() const { 83 CHECK(IsValidManagedRegister()); 84 return (0 <= id_) && (id_ < kNumberOfGpuRegIds); 85 } 86 87 constexpr bool IsFpuRegister() const { 88 CHECK(IsValidManagedRegister()); 89 const int test = id_ - kNumberOfGpuRegIds; 90 return (0 <= test) && (test < kNumberOfFpuRegIds); 91 } 92 93 constexpr bool IsVectorRegister() const { 94 CHECK(IsValidManagedRegister()); 95 const int test = id_ - (kNumberOfGpuRegIds + kNumberOfFpuRegIds); 96 return (0 <= test) && (test < kNumberOfVecRegIds); 97 } 98 99 void Print(std::ostream& os) const; 100 101 // Returns true if the two managed-registers ('this' and 'other') overlap. 102 // Either managed-register may be the NoRegister. If both are the NoRegister 103 // then false is returned. 104 bool Overlaps(const Mips64ManagedRegister& other) const; 105 106 static constexpr Mips64ManagedRegister FromGpuRegister(GpuRegister r) { 107 CHECK_NE(r, kNoGpuRegister); 108 return FromRegId(r); 109 } 110 111 static constexpr Mips64ManagedRegister FromFpuRegister(FpuRegister r) { 112 CHECK_NE(r, kNoFpuRegister); 113 return FromRegId(r + kNumberOfGpuRegIds); 114 } 115 116 static constexpr Mips64ManagedRegister FromVectorRegister(VectorRegister r) { 117 CHECK_NE(r, kNoVectorRegister); 118 return FromRegId(r + kNumberOfGpuRegIds + kNumberOfFpuRegIds); 119 } 120 121 private: 122 constexpr bool IsValidManagedRegister() const { 123 return (0 <= id_) && (id_ < kNumberOfRegIds); 124 } 125 126 constexpr int RegId() const { 127 CHECK(!IsNoRegister()); 128 return id_; 129 } 130 131 int AllocId() const { 132 CHECK(IsValidManagedRegister()); 133 CHECK_LT(id_, kNumberOfAllocIds); 134 return id_; 135 } 136 137 int AllocIdLow() const; 138 int AllocIdHigh() const; 139 140 friend class ManagedRegister; 141 142 explicit constexpr Mips64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} 143 144 static constexpr Mips64ManagedRegister FromRegId(int reg_id) { 145 Mips64ManagedRegister reg(reg_id); 146 CHECK(reg.IsValidManagedRegister()); 147 return reg; 148 } 149 }; 150 151 std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg); 152 153 } // namespace mips64 154 155 constexpr inline mips64::Mips64ManagedRegister ManagedRegister::AsMips64() const { 156 mips64::Mips64ManagedRegister reg(id_); 157 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); 158 return reg; 159 } 160 161 } // namespace art 162 163 #endif // ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_ 164
