| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 70 bool NegAcc, bool HasLane);
274 bool NegAcc, bool HasLane) {
282 unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
283 unsigned NextOp = HasLane ? 5 : 4;
296 if (HasLane)
361 bool NegAcc, HasLane;
363 MulOpc, AddSubOpc, NegAcc, HasLane) ||
367 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
|
| ARMBaseInstrInfo.cpp | 60 bool HasLane; // True if instruction has an extra "lane" operand.
64 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 67 bool NegAcc, bool HasLane);
208 bool NegAcc, bool HasLane) {
216 unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
217 unsigned NextOp = HasLane ? 5 : 4;
228 if (HasLane)
293 bool NegAcc, HasLane;
295 MulOpc, AddSubOpc, NegAcc, HasLane) ||
299 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
|
| ARMBaseInstrInfo.cpp | 59 bool HasLane; // True if instruction has an extra "lane" operand.
63 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 70 bool NegAcc, bool HasLane);
274 bool NegAcc, bool HasLane) {
282 unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
283 unsigned NextOp = HasLane ? 5 : 4;
296 if (HasLane)
358 bool NegAcc, HasLane;
360 MulOpc, AddSubOpc, NegAcc, HasLane) ||
364 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
|
| ARMBaseInstrInfo.cpp | 84 bool HasLane; // True if instruction has an extra "lane" operand.
88 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 317 bool HasLane;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 339 bool HasLane;
[all...] |
