1 /** @file 2 * 3 * Copyright (c) 2015, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2015, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef _I2C_HW_H_ 17 #define _I2C_HW_H_ 18 19 #include <Uefi.h> 20 #include <Library/IoLib.h> 21 22 #define I2C_READ_TIMEOUT 500 23 #define I2C_DRV_ONCE_WRITE_BYTES_NUM 8 24 #define I2C_DRV_ONCE_READ_BYTES_NUM 8 25 #define I2C_READ_SIGNAL 0x0100 26 #define I2C_TXRX_THRESHOLD 0x7 27 #define I2C_SS_SCLHCNT 0x493 28 #define I2C_SS_SCLLCNT 0x4fe 29 #define I2C_CMD_STOP_BIT BIT9 30 31 #define I2C_REG_WRITE(reg,data) \ 32 MmioWrite32 ((reg), (data)) 33 34 #define I2C_REG_READ(reg,result) \ 35 (result) = MmioRead32 ((reg)) 36 37 #define I2C_CON_OFFSET 0x0 38 #define I2C_TAR_OFFSET 0x4 39 #define I2C_SAR_OFFSET 0x8 40 #define I2C_DATA_CMD_OFFSET 0x10 41 #define I2C_SS_SCL_HCNT_OFFSET 0x14 42 #define I2C_SS_SCL_LCNT_OFFSET 0x18 43 #define I2C_FS_SCL_HCNT_OFFSET 0x1c 44 #define I2C_FS_SCL_LCNT_OFFSET 0x20 45 #define I2C_INTR_STAT_OFFSET 0x2c 46 #define I2C_INTR_MASK_OFFSET 0x30 47 #define I2C_RAW_INTR_STAT_OFFSET 0x34 48 #define I2C_RX_TL_OFFSET 0x38 49 #define I2C_TX_TL_OFFSET 0x3c 50 #define I2C_CLR_INTR_OFFSET 0x40 51 #define I2C_CLR_RX_UNDER_OFFSET 0x44 52 #define I2C_CLR_RX_OVER_OFFSET 0x48 53 #define I2C_CLR_TX_OVER_OFFSET 0x4c 54 #define I2C_CLR_RD_REQ_OFFSET 0x50 55 #define I2C_CLR_TX_ABRT_OFFSET 0x54 56 #define I2C_CLR_RX_DONE_OFFSET 0x58 57 #define I2C_CLR_ACTIVITY_OFFSET 0x5c 58 #define I2C_CLR_STOP_DET_OFFSET 0x60 59 #define I2C_CLR_START_DET_OFFSET 0x64 60 #define I2C_CLR_GEN_CALL_OFFSET 0x68 61 #define I2C_ENABLE_OFFSET 0x6c 62 #define I2C_STATUS_OFFSET 0x70 63 #define I2C_TXFLR_OFFSET 0x74 64 #define I2C_RXFLR_OFFSET 0x78 65 #define I2C_SDA_HOLD 0x7c 66 #define I2C_TX_ABRT_SOURCE_OFFSET 0x80 67 #define I2C_SLV_DATA_ONLY_OFFSET 0x84 68 #define I2C_DMA_CR_OFFSET 0x88 69 #define I2C_DMA_TDLR_OFFSET 0x8c 70 #define I2C_DMA_RDLR_OFFSET 0x90 71 #define I2C_SDA_SETUP_OFFSET 0x94 72 #define I2C_ACK_GENERAL_CALL_OFFSET 0x98 73 #define I2C_ENABLE_STATUS_OFFSET 0x9c 74 75 76 typedef union tagI2c0Con 77 { 78 struct 79 { 80 UINT32 master : 1 ; 81 UINT32 spedd : 2 ; 82 UINT32 slave_10bit : 1 ; 83 UINT32 master_10bit : 1 ; 84 UINT32 restart_en : 1 ; 85 UINT32 slave_disable : 1 ; 86 UINT32 Reserved_0 : 25 ; 87 } bits; 88 UINT32 Val32; 89 } I2C0_CON_U; 90 91 92 typedef union tagI2c0Tar 93 { 94 struct 95 { 96 UINT32 ic_tar : 10 ; 97 UINT32 gc_or_start : 1 ; 98 UINT32 special : 1 ; 99 UINT32 ic_10bitaddr_master : 1 ; 100 UINT32 Reserved_1 : 19 ; 101 } bits; 102 UINT32 Val32; 103 } I2C0_TAR_U; 104 105 106 typedef union tagI2c0DataCmd 107 { 108 struct 109 { 110 UINT32 dat : 8 ; 111 UINT32 cmd : 1 ; 112 UINT32 Reserved_5 : 23 ; 113 } bits; 114 UINT32 Val32; 115 } I2C0_DATA_CMD_U; 116 117 118 typedef union tagI2c0SsSclHcnt 119 { 120 struct 121 { 122 UINT32 ic_ss_scl_hcnt : 16 ; 123 UINT32 Reserved_7 : 16 ; 124 } bits; 125 UINT32 Val32; 126 } I2C0_SS_SCL_HCNT_U; 127 128 129 typedef union tagI2c0SsSclLcnt 130 { 131 struct 132 { 133 UINT32 ic_ss_scl_lcnt : 16 ; 134 UINT32 Reserved_9 : 16 ; 135 } bits; 136 UINT32 Val32; 137 } I2C0_SS_SCL_LCNT_U; 138 139 140 typedef union tagI2c0FsSclHcnt 141 { 142 struct 143 { 144 UINT32 ic_fs_scl_hcnt : 16 ; 145 UINT32 Reserved_11 : 16 ; 146 } bits; 147 UINT32 Val32; 148 } I2C0_FS_SCL_HCNT_U; 149 150 151 typedef union tagI2c0FsSclLcnt 152 { 153 struct 154 { 155 UINT32 ic_fs_scl_lcnt : 16 ; 156 UINT32 Reserved_13 : 16 ; 157 } bits; 158 UINT32 Val32; 159 } I2C0_FS_SCL_LCNT_U; 160 161 162 typedef union tagI2c0IntrMask 163 { 164 struct 165 { 166 UINT32 m_rx_under : 1 ; 167 UINT32 m_rx_over : 1 ; 168 UINT32 m_rx_full : 1 ; 169 UINT32 m_tx_over : 1 ; 170 UINT32 m_tx_empty : 1 ; 171 UINT32 m_rd_req : 1 ; 172 UINT32 m_tx_abrt : 1 ; 173 UINT32 m_rx_done : 1 ; 174 UINT32 m_activity : 1 ; 175 UINT32 m_stop_det : 1 ; 176 UINT32 m_start_det : 1 ; 177 UINT32 m_gen_call : 1 ; 178 UINT32 Reserved_17 : 20 ; 179 } bits; 180 UINT32 Val32; 181 } I2C0_INTR_MASK_U; 182 183 184 typedef union tagI2c0RxTl 185 { 186 struct 187 { 188 UINT32 rx_tl : 8 ; 189 UINT32 Reserved_21 : 24 ; 190 } bits; 191 UINT32 Val32; 192 } I2C0_RX_TL_U; 193 194 195 typedef union tagI2c0TxTl 196 { 197 struct 198 { 199 UINT32 tx_tl : 8 ; 200 UINT32 Reserved_23 : 24 ; 201 } bits; 202 UINT32 Val32; 203 } I2C0_TX_TL_U; 204 205 206 typedef union tagI2c0Enable 207 { 208 struct 209 { 210 UINT32 enable : 1 ; 211 UINT32 Reserved_47 : 31 ; 212 } bits; 213 UINT32 Val32; 214 } I2C0_ENABLE_U; 215 216 217 typedef union tagI2c0Status 218 { 219 struct 220 { 221 UINT32 activity : 1 ; 222 UINT32 tfnf : 1 ; 223 UINT32 tfe : 1 ; 224 UINT32 rfne : 1 ; 225 UINT32 rff : 1 ; 226 UINT32 mst_activity : 1 ; 227 UINT32 slv_activity : 1 ; 228 UINT32 Reserved_49 : 25 ; 229 } bits; 230 UINT32 Val32; 231 } I2C0_STATUS_U; 232 233 234 typedef union tagI2c0Txflr 235 { 236 struct 237 { 238 UINT32 txflr : 4 ; 239 UINT32 Reserved_51 : 28 ; 240 } bits; 241 UINT32 Val32; 242 } I2C0_TXFLR_U; 243 244 245 typedef union tagI2c0Rxflr 246 { 247 struct 248 { 249 UINT32 rxflr : 4 ; 250 UINT32 Reserved_53 : 28 ; 251 } bits; 252 UINT32 Val32; 253 } I2C0_RXFLR_U; 254 255 256 typedef union tagI2c0EnableStatus 257 { 258 struct 259 { 260 UINT32 ic_en : 1 ; 261 UINT32 slv_disable_while_busy: 1 ; 262 UINT32 slv_rx_data_lost : 1 ; 263 UINT32 Reserved_69 : 29 ; 264 } bits; 265 UINT32 Val32; 266 } I2C0_ENABLE_STATUS_U; 267 268 269 #endif 270
