1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung (at) samsung.com> 5 */ 6 7 #ifndef __ASM_ARCH_I2C_H 8 #define __ASM_ARCH_I2C_H 9 10 struct i2c_regs { 11 u32 con; 12 u32 clkdiv; 13 u32 mrxaddr; 14 u32 mrxraddr; 15 u32 mtxcnt; 16 u32 mrxcnt; 17 u32 ien; 18 u32 ipd; 19 u32 fcnt; 20 u32 reserved0[0x37]; 21 u32 txdata[8]; 22 u32 reserved1[0x38]; 23 u32 rxdata[8]; 24 }; 25 26 /* Control register */ 27 #define I2C_CON_EN (1 << 0) 28 #define I2C_CON_MOD(mod) ((mod) << 1) 29 #define I2C_MODE_TX 0x00 30 #define I2C_MODE_TRX 0x01 31 #define I2C_MODE_RX 0x02 32 #define I2C_MODE_RRX 0x03 33 #define I2C_CON_MASK (3 << 1) 34 35 #define I2C_CON_START (1 << 3) 36 #define I2C_CON_STOP (1 << 4) 37 #define I2C_CON_LASTACK (1 << 5) 38 #define I2C_CON_ACTACK (1 << 6) 39 40 /* Clock dividor register */ 41 #define I2C_CLKDIV_VAL(divl, divh) \ 42 (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) 43 44 /* the slave address accessed for master rx mode */ 45 #define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) 46 47 /* the slave register address accessed for master rx mode */ 48 #define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) 49 50 /* interrupt enable register */ 51 #define I2C_BTFIEN (1 << 0) 52 #define I2C_BRFIEN (1 << 1) 53 #define I2C_MBTFIEN (1 << 2) 54 #define I2C_MBRFIEN (1 << 3) 55 #define I2C_STARTIEN (1 << 4) 56 #define I2C_STOPIEN (1 << 5) 57 #define I2C_NAKRCVIEN (1 << 6) 58 59 /* interrupt pending register */ 60 #define I2C_BTFIPD (1 << 0) 61 #define I2C_BRFIPD (1 << 1) 62 #define I2C_MBTFIPD (1 << 2) 63 #define I2C_MBRFIPD (1 << 3) 64 #define I2C_STARTIPD (1 << 4) 65 #define I2C_STOPIPD (1 << 5) 66 #define I2C_NAKRCVIPD (1 << 6) 67 #define I2C_IPD_ALL_CLEAN 0x7f 68 69 #endif 70
