1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file provides WebAssembly-specific target descriptions. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 17 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCContext; 28 class MCInstrInfo; 29 class MCObjectTargetWriter; 30 class MCSubtargetInfo; 31 class MVT; 32 class Target; 33 class Triple; 34 class raw_pwrite_stream; 35 36 Target &getTheWebAssemblyTarget32(); 37 Target &getTheWebAssemblyTarget64(); 38 39 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 40 41 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 42 43 std::unique_ptr<MCObjectTargetWriter> 44 createWebAssemblyWasmObjectWriter(bool Is64Bit); 45 46 namespace WebAssembly { 47 enum OperandType { 48 /// Basic block label in a branch construct. 49 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 50 /// Local index. 51 OPERAND_LOCAL, 52 /// Global index. 53 OPERAND_GLOBAL, 54 /// 32-bit integer immediates. 55 OPERAND_I32IMM, 56 /// 64-bit integer immediates. 57 OPERAND_I64IMM, 58 /// 32-bit floating-point immediates. 59 OPERAND_F32IMM, 60 /// 64-bit floating-point immediates. 61 OPERAND_F64IMM, 62 /// 32-bit unsigned function indices. 63 OPERAND_FUNCTION32, 64 /// 32-bit unsigned memory offsets. 65 OPERAND_OFFSET32, 66 /// p2align immediate for load and store address alignment. 67 OPERAND_P2ALIGN, 68 /// signature immediate for block/loop. 69 OPERAND_SIGNATURE, 70 /// type signature immediate for call_indirect. 71 OPERAND_TYPEINDEX, 72 }; 73 } // end namespace WebAssembly 74 75 namespace WebAssemblyII { 76 enum { 77 // For variadic instructions, this flag indicates whether an operand 78 // in the variable_ops range is an immediate value. 79 VariableOpIsImmediate = (1 << 0), 80 // For immediate values in the variable_ops range, this flag indicates 81 // whether the value represents a control-flow label. 82 VariableOpImmediateIsLabel = (1 << 1) 83 }; 84 } // end namespace WebAssemblyII 85 86 } // end namespace llvm 87 88 // Defines symbolic names for WebAssembly registers. This defines a mapping from 89 // register name to register number. 90 // 91 #define GET_REGINFO_ENUM 92 #include "WebAssemblyGenRegisterInfo.inc" 93 94 // Defines symbolic names for the WebAssembly instructions. 95 // 96 #define GET_INSTRINFO_ENUM 97 #include "WebAssemblyGenInstrInfo.inc" 98 99 #define GET_SUBTARGETINFO_ENUM 100 #include "WebAssemblyGenSubtargetInfo.inc" 101 102 namespace llvm { 103 namespace WebAssembly { 104 105 /// Return the default p2align value for a load or store with the given opcode. 106 inline unsigned GetDefaultP2Align(unsigned Opcode) { 107 switch (Opcode) { 108 case WebAssembly::LOAD8_S_I32: 109 case WebAssembly::LOAD8_S_I32_S: 110 case WebAssembly::LOAD8_U_I32: 111 case WebAssembly::LOAD8_U_I32_S: 112 case WebAssembly::LOAD8_S_I64: 113 case WebAssembly::LOAD8_S_I64_S: 114 case WebAssembly::LOAD8_U_I64: 115 case WebAssembly::LOAD8_U_I64_S: 116 case WebAssembly::ATOMIC_LOAD8_U_I32: 117 case WebAssembly::ATOMIC_LOAD8_U_I32_S: 118 case WebAssembly::ATOMIC_LOAD8_U_I64: 119 case WebAssembly::ATOMIC_LOAD8_U_I64_S: 120 case WebAssembly::STORE8_I32: 121 case WebAssembly::STORE8_I32_S: 122 case WebAssembly::STORE8_I64: 123 case WebAssembly::STORE8_I64_S: 124 case WebAssembly::ATOMIC_STORE8_I32: 125 case WebAssembly::ATOMIC_STORE8_I32_S: 126 case WebAssembly::ATOMIC_STORE8_I64: 127 case WebAssembly::ATOMIC_STORE8_I64_S: 128 case WebAssembly::ATOMIC_RMW8_U_ADD_I32: 129 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S: 130 case WebAssembly::ATOMIC_RMW8_U_ADD_I64: 131 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S: 132 case WebAssembly::ATOMIC_RMW8_U_SUB_I32: 133 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S: 134 case WebAssembly::ATOMIC_RMW8_U_SUB_I64: 135 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S: 136 case WebAssembly::ATOMIC_RMW8_U_AND_I32: 137 case WebAssembly::ATOMIC_RMW8_U_AND_I32_S: 138 case WebAssembly::ATOMIC_RMW8_U_AND_I64: 139 case WebAssembly::ATOMIC_RMW8_U_AND_I64_S: 140 case WebAssembly::ATOMIC_RMW8_U_OR_I32: 141 case WebAssembly::ATOMIC_RMW8_U_OR_I32_S: 142 case WebAssembly::ATOMIC_RMW8_U_OR_I64: 143 case WebAssembly::ATOMIC_RMW8_U_OR_I64_S: 144 case WebAssembly::ATOMIC_RMW8_U_XOR_I32: 145 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S: 146 case WebAssembly::ATOMIC_RMW8_U_XOR_I64: 147 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S: 148 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32: 149 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S: 150 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64: 151 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S: 152 return 0; 153 case WebAssembly::LOAD16_S_I32: 154 case WebAssembly::LOAD16_S_I32_S: 155 case WebAssembly::LOAD16_U_I32: 156 case WebAssembly::LOAD16_U_I32_S: 157 case WebAssembly::LOAD16_S_I64: 158 case WebAssembly::LOAD16_S_I64_S: 159 case WebAssembly::LOAD16_U_I64: 160 case WebAssembly::LOAD16_U_I64_S: 161 case WebAssembly::ATOMIC_LOAD16_U_I32: 162 case WebAssembly::ATOMIC_LOAD16_U_I32_S: 163 case WebAssembly::ATOMIC_LOAD16_U_I64: 164 case WebAssembly::ATOMIC_LOAD16_U_I64_S: 165 case WebAssembly::STORE16_I32: 166 case WebAssembly::STORE16_I32_S: 167 case WebAssembly::STORE16_I64: 168 case WebAssembly::STORE16_I64_S: 169 case WebAssembly::ATOMIC_STORE16_I32: 170 case WebAssembly::ATOMIC_STORE16_I32_S: 171 case WebAssembly::ATOMIC_STORE16_I64: 172 case WebAssembly::ATOMIC_STORE16_I64_S: 173 case WebAssembly::ATOMIC_RMW16_U_ADD_I32: 174 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S: 175 case WebAssembly::ATOMIC_RMW16_U_ADD_I64: 176 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S: 177 case WebAssembly::ATOMIC_RMW16_U_SUB_I32: 178 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S: 179 case WebAssembly::ATOMIC_RMW16_U_SUB_I64: 180 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S: 181 case WebAssembly::ATOMIC_RMW16_U_AND_I32: 182 case WebAssembly::ATOMIC_RMW16_U_AND_I32_S: 183 case WebAssembly::ATOMIC_RMW16_U_AND_I64: 184 case WebAssembly::ATOMIC_RMW16_U_AND_I64_S: 185 case WebAssembly::ATOMIC_RMW16_U_OR_I32: 186 case WebAssembly::ATOMIC_RMW16_U_OR_I32_S: 187 case WebAssembly::ATOMIC_RMW16_U_OR_I64: 188 case WebAssembly::ATOMIC_RMW16_U_OR_I64_S: 189 case WebAssembly::ATOMIC_RMW16_U_XOR_I32: 190 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S: 191 case WebAssembly::ATOMIC_RMW16_U_XOR_I64: 192 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S: 193 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32: 194 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S: 195 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64: 196 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S: 197 return 1; 198 case WebAssembly::LOAD_I32: 199 case WebAssembly::LOAD_I32_S: 200 case WebAssembly::LOAD_F32: 201 case WebAssembly::LOAD_F32_S: 202 case WebAssembly::STORE_I32: 203 case WebAssembly::STORE_I32_S: 204 case WebAssembly::STORE_F32: 205 case WebAssembly::STORE_F32_S: 206 case WebAssembly::LOAD32_S_I64: 207 case WebAssembly::LOAD32_S_I64_S: 208 case WebAssembly::LOAD32_U_I64: 209 case WebAssembly::LOAD32_U_I64_S: 210 case WebAssembly::STORE32_I64: 211 case WebAssembly::STORE32_I64_S: 212 case WebAssembly::ATOMIC_LOAD_I32: 213 case WebAssembly::ATOMIC_LOAD_I32_S: 214 case WebAssembly::ATOMIC_LOAD32_U_I64: 215 case WebAssembly::ATOMIC_LOAD32_U_I64_S: 216 case WebAssembly::ATOMIC_STORE_I32: 217 case WebAssembly::ATOMIC_STORE_I32_S: 218 case WebAssembly::ATOMIC_STORE32_I64: 219 case WebAssembly::ATOMIC_STORE32_I64_S: 220 case WebAssembly::ATOMIC_RMW_ADD_I32: 221 case WebAssembly::ATOMIC_RMW_ADD_I32_S: 222 case WebAssembly::ATOMIC_RMW32_U_ADD_I64: 223 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S: 224 case WebAssembly::ATOMIC_RMW_SUB_I32: 225 case WebAssembly::ATOMIC_RMW_SUB_I32_S: 226 case WebAssembly::ATOMIC_RMW32_U_SUB_I64: 227 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S: 228 case WebAssembly::ATOMIC_RMW_AND_I32: 229 case WebAssembly::ATOMIC_RMW_AND_I32_S: 230 case WebAssembly::ATOMIC_RMW32_U_AND_I64: 231 case WebAssembly::ATOMIC_RMW32_U_AND_I64_S: 232 case WebAssembly::ATOMIC_RMW_OR_I32: 233 case WebAssembly::ATOMIC_RMW_OR_I32_S: 234 case WebAssembly::ATOMIC_RMW32_U_OR_I64: 235 case WebAssembly::ATOMIC_RMW32_U_OR_I64_S: 236 case WebAssembly::ATOMIC_RMW_XOR_I32: 237 case WebAssembly::ATOMIC_RMW_XOR_I32_S: 238 case WebAssembly::ATOMIC_RMW32_U_XOR_I64: 239 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S: 240 case WebAssembly::ATOMIC_RMW_XCHG_I32: 241 case WebAssembly::ATOMIC_RMW_XCHG_I32_S: 242 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64: 243 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S: 244 return 2; 245 case WebAssembly::LOAD_I64: 246 case WebAssembly::LOAD_I64_S: 247 case WebAssembly::LOAD_F64: 248 case WebAssembly::LOAD_F64_S: 249 case WebAssembly::STORE_I64: 250 case WebAssembly::STORE_I64_S: 251 case WebAssembly::STORE_F64: 252 case WebAssembly::STORE_F64_S: 253 case WebAssembly::ATOMIC_LOAD_I64: 254 case WebAssembly::ATOMIC_LOAD_I64_S: 255 case WebAssembly::ATOMIC_STORE_I64: 256 case WebAssembly::ATOMIC_STORE_I64_S: 257 case WebAssembly::ATOMIC_RMW_ADD_I64: 258 case WebAssembly::ATOMIC_RMW_ADD_I64_S: 259 case WebAssembly::ATOMIC_RMW_SUB_I64: 260 case WebAssembly::ATOMIC_RMW_SUB_I64_S: 261 case WebAssembly::ATOMIC_RMW_AND_I64: 262 case WebAssembly::ATOMIC_RMW_AND_I64_S: 263 case WebAssembly::ATOMIC_RMW_OR_I64: 264 case WebAssembly::ATOMIC_RMW_OR_I64_S: 265 case WebAssembly::ATOMIC_RMW_XOR_I64: 266 case WebAssembly::ATOMIC_RMW_XOR_I64_S: 267 case WebAssembly::ATOMIC_RMW_XCHG_I64: 268 case WebAssembly::ATOMIC_RMW_XCHG_I64_S: 269 return 3; 270 default: 271 llvm_unreachable("Only loads and stores have p2align values"); 272 } 273 } 274 275 /// The operand number of the load or store address in load/store instructions. 276 static const unsigned LoadAddressOperandNo = 3; 277 static const unsigned StoreAddressOperandNo = 2; 278 279 /// The operand number of the load or store p2align in load/store instructions. 280 static const unsigned LoadP2AlignOperandNo = 1; 281 static const unsigned StoreP2AlignOperandNo = 0; 282 283 /// This is used to indicate block signatures. 284 enum class ExprType : unsigned { 285 Void = 0x40, 286 I32 = 0x7F, 287 I64 = 0x7E, 288 F32 = 0x7D, 289 F64 = 0x7C, 290 I8x16 = 0x7B, 291 I16x8 = 0x7A, 292 I32x4 = 0x79, 293 F32x4 = 0x78, 294 B8x16 = 0x77, 295 B16x8 = 0x76, 296 B32x4 = 0x75, 297 ExceptRef = 0x68 298 }; 299 300 /// Instruction opcodes emitted via means other than CodeGen. 301 static const unsigned Nop = 0x01; 302 static const unsigned End = 0x0b; 303 304 wasm::ValType toValType(const MVT &Ty); 305 306 } // end namespace WebAssembly 307 } // end namespace llvm 308 309 #endif 310
