1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef __ASM_ARCH_IOMUX_H__ 4 #define __ASM_ARCH_IOMUX_H__ 5 6 #define MX6_IOMUXC_GPR4 0x020e0010 7 #define MX6_IOMUXC_GPR6 0x020e0018 8 #define MX6_IOMUXC_GPR7 0x020e001c 9 10 /* 11 * IOMUXC_GPR1 bit fields 12 */ 13 #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) 14 #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) 15 #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) 16 #define IOMUXC_GPR1_REF_SSP_EN (1 << 16) 17 #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) 18 19 #define IOMUXC_GPR1_PCIE_SW_RST (1 << 29) 20 21 /* 22 * IOMUXC_GPR5 bit fields 23 */ 24 #define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) 25 #define IOMUXC_GPR5_PCIE_PERST (1 << 18) 26 27 /* 28 * IOMUXC_GPR8 bit fields 29 */ 30 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) 31 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 32 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) 33 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 34 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) 35 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 36 #define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) 37 #define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 38 #define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) 39 #define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 40 41 /* 42 * IOMUXC_GPR12 bit fields 43 */ 44 #define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) 45 #define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) 46 #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) 47 #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) 48 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) 49 #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) 50 #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) 51 #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) 52 #define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) 53 54 /* 55 * IOMUXC_GPR13 bit fields 56 */ 57 #define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) 58 #define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) 59 #define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) 60 #define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) 61 #define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) 62 #define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) 63 #define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 64 #define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) 65 #define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15) 66 #define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14) 67 #define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11) 68 #define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7) 69 #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) 70 #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) 71 72 #define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) 73 #define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) 74 #define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ 75 | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) 76 77 #define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17) 78 #define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13) 79 #define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \ 80 | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK) 81 82 #define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18) 83 #define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14) 84 #define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \ 85 | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK) 86 87 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) 88 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) 89 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) 90 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) 91 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) 92 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) 93 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) 94 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) 95 96 #define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) 97 #define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) 98 #define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) 99 #define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) 100 #define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) 101 #define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) 102 103 #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) 104 #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) 105 106 #define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14) 107 #define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14) 108 109 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11) 110 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11) 111 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11) 112 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11) 113 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) 114 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) 115 116 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) 117 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) 118 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) 119 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) 120 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) 121 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) 122 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) 123 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) 124 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) 125 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) 126 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) 127 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) 128 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) 129 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) 130 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) 131 #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) 132 133 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) 134 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) 135 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) 136 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) 137 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) 138 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) 139 #define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) 140 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) 141 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) 142 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) 143 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) 144 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) 145 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) 146 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) 147 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) 148 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) 149 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) 150 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) 151 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) 152 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) 153 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) 154 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) 155 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) 156 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) 157 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) 158 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) 159 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) 160 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) 161 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) 162 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) 163 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) 164 #define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) 165 166 #define IOMUXC_GPR13_SATA_PHY_1_FAST 0 167 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 168 #define IOMUXC_GPR13_SATA_PHY_1_SLOW 2 169 170 #define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \ 171 |IOMUXC_GPR13_SATA_PHY_7_MASK \ 172 |IOMUXC_GPR13_SATA_PHY_6_MASK \ 173 |IOMUXC_GPR13_SATA_SPEED_MASK \ 174 |IOMUXC_GPR13_SATA_PHY_5_MASK \ 175 |IOMUXC_GPR13_SATA_PHY_4_MASK \ 176 |IOMUXC_GPR13_SATA_PHY_3_MASK \ 177 |IOMUXC_GPR13_SATA_PHY_2_MASK \ 178 |IOMUXC_GPR13_SATA_PHY_1_MASK) 179 180 /* 181 * Setup RGMII voltage levels on iMX6 SoC - the 182 * 183 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register 184 * 185 * 1P2V_IO - USB_HSIC, MIPI_HSI 186 * 1P5V_IO - ENET pins 187 */ 188 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x020e0790 189 #define DDR_SEL_1P2V_IO (0x2 << 18) 190 #define DDR_SEL_1P5V_IO (0x3 << 18) 191 192 #endif /* __ASM_ARCH_IOMUX_H__ */ 193
