| /external/swiftshader/third_party/LLVM/tools/llvm-objdump/ |
| MCFunction.cpp | 35 std::vector<MCDecodedInst> Instructions;
57 Instructions.push_back(MCDecodedInst(Index, Size, Inst));
92 std::sort(Instructions.begin(), Instructions.end());
95 unsigned ii = 0, ie = Instructions.size();
100 // Add instructions to the BB.
102 if (Instructions[ii].Address < *spi ||
103 Instructions[ii].Address >= BlockEnd)
105 BB.addInst(Instructions[ii]);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| InstructionInfoView.cpp | 25 unsigned Instructions = Source.size();
34 TempStream << "[1] [2] [3] [4] [5] [6] Instructions:\n";
35 for (unsigned I = 0, E = Instructions; I < E; ++I) {
|
| SummaryView.cpp | 37 // the dispatch stage for instructions that are part of iteration #0.
64 unsigned Instructions = Source.size();
65 unsigned TotalInstructions = Instructions * Iterations;
|
| CodeRegion.h | 47 /// It identifies a sequence of machine instructions.
51 // Instructions that form this region.
52 std::vector<std::unique_ptr<const llvm::MCInst>> Instructions;
65 Instructions.emplace_back(std::move(Instruction));
72 bool empty() const { return Instructions.empty(); }
77 return Instructions;
|
| /external/v8/src/compiler/ |
| move-optimizer.h | 23 typedef ZoneVector<Instruction*> Instructions;
|
| /external/llvm/include/llvm/MC/ |
| MCWinEH.h | 45 std::vector<Instruction> Instructions;
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCWin64EH.h | 68 Instructions() {}
79 std::vector<MCWin64EHInstruction> Instructions;
|
| MCDwarf.h | 176 /// for a section where machine instructions have been assembled after seeing
265 Function(0), Instructions(), PersonalityEncoding(),
272 std::vector<MCCFIInstruction> Instructions;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| MCWinEH.h | 45 std::vector<Instruction> Instructions;
|
| /art/libdexfile/dex/ |
| dex_instruction_iterator.h | 43 ALWAYS_INLINE const uint16_t* Instructions() const {
48 explicit DexInstructionPcPair(const uint16_t* instructions, uint32_t dex_pc)
49 : instructions_(instructions), dex_pc_(dex_pc) {}
78 // Instructions from the start of the code item.
79 ALWAYS_INLINE const uint16_t* Instructions() const {
80 return data_.Instructions();
89 DCHECK_EQ(lhs.Instructions(), rhs.Instructions()) << "Comparing different code items.";
100 DCHECK_EQ(lhs.Instructions(), rhs.Instructions()) << "Comparing different code items."
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| BenchmarkResult.h | 35 std::vector<llvm::MCInst> Instructions;
54 // The number of instructions inside the repeated snippet. For example, if a
55 // snippet of 3 instructions is repeated 4 times, this is 12.
106 // that Registers and Instructions are human readable and preserved accross
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| CodeGenTarget.h | 53 std::unique_ptr<CodeGenInstruction>> Instructions;
137 if (Instructions.empty()) ReadInstructions();
138 return Instructions;
143 if (Instructions.empty()) ReadInstructions();
144 auto I = Instructions.find(InstRec);
145 assert(I != Instructions.end() && "Not an instruction");
149 /// Returns the number of predefined instructions.
152 /// Returns the number of pseudo instructions.
159 /// Return all of the instructions defined by the target, ordered by their
161 /// The following order of instructions is also guaranteed
[all...] |
| /external/llvm/lib/DebugInfo/DWARF/ |
| DWARFDebugFrame.cpp | 44 /// \brief Parse and store a sequence of CFI instructions from Data,
54 /// \brief Dump the entry's instructions to the given output stream.
66 /// An entry may contain CFI instructions. An instruction consists of an
78 std::vector<Instruction> Instructions;
81 /// operands to the Instructions vector.
83 Instructions.push_back(Instruction(Opcode));
87 Instructions.push_back(Instruction(Opcode));
88 Instructions.back().Ops.push_back(Operand1);
92 Instructions.push_back(Instruction(Opcode));
93 Instructions.back().Ops.push_back(Operand1)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 37 #include "llvm/IR/Instructions.h"
84 // sext instructions.
103 typedef SmallVector<Instruction *, 16> Instructions;
104 typedef DenseMap<Value *, Instructions> ValueToInsts;
121 /// Move sext operations through safe to sext instructions.
122 bool propagateSignExtension(Instructions &SExtInsts);
136 void analyzeSExtension(Instructions &SExtInsts);
226 // - SExtInsts contains all the sext instructions that are used directly in
251 AArch64AddressTypePromotion::propagateSignExtension(Instructions &SExtInsts) {
344 // If more sext are required, new instructions will have to be created
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIWholeQuadMode.cpp | 11 /// \brief This pass adds instructions to enable whole quad mode for pixel
26 /// instructions by
33 /// instructions, the pass first analyzes which instructions must be run in WQM
34 /// (aka which instructions produce values that lead to derivative
46 /// consist of exact and don't-care instructions, the switch only has to
98 DenseMap<const MachineInstr *, InstrInfo> Instructions;
147 // Scan instructions to determine which ones require an Exact execmask and
167 // Handle export instructions with the exec mask valid flag set
195 Instructions[&MI].Needs = Flags
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCodeEmitter.cpp | 33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
112 // Compound instructions are limited to using registers 0-7 and 16-23
118 // Pseudo instructions don't get encoded and shouldn't be here
145 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
146 auto i = Instructions.begin() + Index - 1;
148 assert(i != Instructions.begin() - 1 && "Couldn't find producer");
154 // Vector instructions don't count scalars
187 // Check for unimplemented instructions. Immediate extenders
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.h | 69 std::unique_ptr<CodeGenInstruction>> Instructions;
150 if (Instructions.empty()) ReadInstructions();
151 return Instructions;
156 if (Instructions.empty()) ReadInstructions();
157 auto I = Instructions.find(InstRec);
158 assert(I != Instructions.end() && "Not an instruction");
162 /// getInstructionsByEnumValue - Return all of the instructions defined by the
180 /// encodings, reverse the bit order of all instructions.
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_deadcode.c | 61 struct instruction_state * Instructions;
155 struct instruction_state * insts = &s->Instructions[inst->IP];
225 s.Instructions = memory_pool_malloc(&c->Pool, sizeof(struct instruction_state)*nr_instructions);
226 memset(s.Instructions, 0, sizeof(struct instruction_state)*nr_instructions);
230 for(struct rc_instruction * inst = c->Program.Instructions.Prev;
231 inst != &c->Program.Instructions;
313 for(struct rc_instruction * inst = c->Program.Instructions.Next;
314 inst != &c->Program.Instructions;
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
325 if (s.Instructions[ip].WriteMask
[all...] |
| radeon_program.h | 70 * Instructions are maintained by the compiler in a doubly linked list
101 * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
153 * Instructions.Next points to the first instruction,
154 * Instructions.Prev points to the last instruction.
156 struct rc_instruction Instructions;
|
| /external/swiftshader/third_party/LLVM/tools/bugpoint/ |
| CrashDebugger.cpp | 19 #include "llvm/Instructions.h"
357 /// non-terminator instructions and replacing them with undef.
388 SmallPtrSet<Instruction*, 64> Instructions;
391 Instructions.insert(cast<Instruction>(VMap[Insts[i]]));
394 outs() << "Checking for crash with only " << Instructions.size();
395 if (Instructions.size() == 1)
398 outs() << " instructions: ";
404 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst)) {
423 for (SmallPtrSet<Instruction*, 64>::const_iterator I = Instructions.begin(),
424 E = Instructions.end(); I != E; ++I)
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenTarget.h | 67 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
134 if (Instructions.empty()) ReadInstructions();
135 return Instructions;
140 if (Instructions.empty()) ReadInstructions();
142 Instructions.find(InstRec);
143 assert(I != Instructions.end() && "Not an instruction");
147 /// getInstructionsByEnumValue - Return all of the instructions defined by the
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| X86WinCOFFTargetStreamer.cpp | 62 SmallVector<FPOInstruction, 5> Instructions;
179 // Complain if there were prologue setup instructions but no end prologue.
180 if (!CurFPOData->Instructions.empty()) {
182 CurFPOData->Instructions.clear();
203 CurFPOData->Instructions.push_back(Inst);
214 CurFPOData->Instructions.push_back(Inst);
225 CurFPOData->Instructions.push_back(Inst);
372 for (const FPOInstruction &Inst : FPO->Instructions) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-cfi-verify/lib/ |
| FileAnalysis.h | 74 // sequential control flows, including indirect control flow instructions.
114 // Undefined (and bad) instructions cannot fall through, and instruction that
137 // Returns the list of indirect instructions.
213 std::map<uint64_t, Instr> Instructions;
215 // Contains a mapping between a specific address, and a list of instructions
216 // that use this address as a branch target (including call instructions).
219 // A list of addresses of indirect control flow instructions.
|
| /external/llvm/tools/bugpoint/ |
| CrashDebugger.cpp | 22 #include "llvm/IR/Instructions.h"
432 /// non-terminator instructions and replacing them with undef.
463 SmallPtrSet<Instruction*, 32> Instructions;
466 Instructions.insert(cast<Instruction>(VMap[Insts[i]]));
469 outs() << "Checking for crash with only " << Instructions.size();
470 if (Instructions.size() == 1)
473 outs() << " instructions: ";
479 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst) &&
499 for (Instruction *Inst : Instructions)
709 // Attempt to delete instructions using bisection. This should help out nast
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/DebugInfo/DWARF/ |
| DWARFDebugFrame.h | 28 /// Represent a sequence of Call Frame Information instructions that, when read
54 iterator begin() { return Instructions.begin(); }
55 const_iterator begin() const { return Instructions.begin(); }
56 iterator end() { return Instructions.end(); }
57 const_iterator end() const { return Instructions.end(); }
59 unsigned size() const { return (unsigned)Instructions.size(); }
60 bool empty() const { return Instructions.empty(); }
66 /// Parse and store a sequence of CFI instructions from Data,
76 std::vector<Instruction> Instructions;
82 Instructions.push_back(Instruction(Opcode))
[all...] |
