1 /** @file 2 * 3 * Copyright (c) 2012-2014, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __LAN9118_DXE_HW_H__ 16 #define __LAN9118_DXE_HW_H__ 17 18 /*------------------------------------------------------------------------------ 19 LAN9118 SMCS Registers 20 ------------------------------------------------------------------------------*/ 21 22 // Base address as on the VE board 23 #define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress)) 24 25 /* ------------- Tx and Rx Data and Status Memory Locations ------------------*/ 26 #define LAN9118_RX_DATA (0x00000000 + LAN9118_BA) 27 #define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA) 28 #define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA) 29 #define LAN9118_TX_DATA (0x00000020 + LAN9118_BA) 30 #define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA) 31 #define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA) 32 33 /* ------------- System Control and Status Registers -------------------------*/ 34 #define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision 35 #define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration 36 #define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status 37 #define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable 38 //#define LAN9118_RESERVED (0x00000060) 39 #define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test 40 #define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts 41 #define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration 42 #define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration 43 #define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration 44 #define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration 45 #define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information 46 #define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information 47 #define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control 48 #define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration 49 #define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration 50 #define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count 51 #define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control 52 #define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter 53 #define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter 54 #define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command 55 #define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data 56 #define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration 57 #define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command 58 #define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data 59 60 /* 61 * Required delays following write cycles (number of BYTE_TEST reads) 62 * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet. 63 * Where no delay listed, 0 has been assumed. 64 */ 65 #define LAN9118_RX_DATA_WR_DELAY 0 66 #define LAN9118_RX_STATUS_WR_DELAY 0 67 #define LAN9118_RX_STATUS_PEEK_WR_DELAY 0 68 #define LAN9118_TX_DATA_WR_DELAY 0 69 #define LAN9118_TX_STATUS_WR_DELAY 0 70 #define LAN9118_TX_STATUS_PEEK_WR_DELAY 0 71 #define LAN9118_ID_REV_WR_DELAY 0 72 #define LAN9118_IRQ_CFG_WR_DELAY 3 73 #define LAN9118_INT_STS_WR_DELAY 2 74 #define LAN9118_INT_EN_WR_DELAY 1 75 #define LAN9118_BYTE_TEST_WR_DELAY 0 76 #define LAN9118_FIFO_INT_WR_DELAY 1 77 #define LAN9118_RX_CFG_WR_DELAY 1 78 #define LAN9118_TX_CFG_WR_DELAY 1 79 #define LAN9118_HW_CFG_WR_DELAY 1 80 #define LAN9118_RX_DP_CTL_WR_DELAY 1 81 #define LAN9118_RX_FIFO_INF_WR_DELAY 0 82 #define LAN9118_TX_FIFO_INF_WR_DELAY 3 83 #define LAN9118_PMT_CTRL_WR_DELAY 7 84 #define LAN9118_GPIO_CFG_WR_DELAY 1 85 #define LAN9118_GPT_CFG_WR_DELAY 1 86 #define LAN9118_GPT_CNT_WR_DELAY 3 87 #define LAN9118_WORD_SWAP_WR_DELAY 1 88 #define LAN9118_FREE_RUN_WR_DELAY 4 89 #define LAN9118_RX_DROP_WR_DELAY 0 90 #define LAN9118_MAC_CSR_CMD_WR_DELAY 1 91 #define LAN9118_MAC_CSR_DATA_WR_DELAY 1 92 #define LAN9118_AFC_CFG_WR_DELAY 1 93 #define LAN9118_E2P_CMD_WR_DELAY 1 94 #define LAN9118_E2P_DATA_WR_DELAY 1 95 96 /* 97 * Required delays following read cycles (number of BYTE_TEST reads) 98 * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet. 99 * Where no delay listed, 0 has been assumed. 100 */ 101 #define LAN9118_RX_DATA_RD_DELAY 3 102 #define LAN9118_RX_STATUS_RD_DELAY 3 103 #define LAN9118_RX_STATUS_PEEK_RD_DELAY 0 104 #define LAN9118_TX_DATA_RD_DELAY 0 105 #define LAN9118_TX_STATUS_RD_DELAY 3 106 #define LAN9118_TX_STATUS_PEEK_RD_DELAY 0 107 #define LAN9118_ID_REV_RD_DELAY 0 108 #define LAN9118_IRQ_CFG_RD_DELAY 0 109 #define LAN9118_INT_STS_RD_DELAY 0 110 #define LAN9118_INT_EN_RD_DELAY 0 111 #define LAN9118_BYTE_TEST_RD_DELAY 0 112 #define LAN9118_FIFO_INT_RD_DELAY 0 113 #define LAN9118_RX_CFG_RD_DELAY 0 114 #define LAN9118_TX_CFG_RD_DELAY 0 115 #define LAN9118_HW_CFG_RD_DELAY 0 116 #define LAN9118_RX_DP_CTL_RD_DELAY 0 117 #define LAN9118_RX_FIFO_INF_RD_DELAY 0 118 #define LAN9118_TX_FIFO_INF_RD_DELAY 0 119 #define LAN9118_PMT_CTRL_RD_DELAY 0 120 #define LAN9118_GPIO_CFG_RD_DELAY 0 121 #define LAN9118_GPT_CFG_RD_DELAY 0 122 #define LAN9118_GPT_CNT_RD_DELAY 0 123 #define LAN9118_WORD_SWAP_RD_DELAY 0 124 #define LAN9118_FREE_RUN_RD_DELAY 0 125 #define LAN9118_RX_DROP_RD_DELAY 4 126 #define LAN9118_MAC_CSR_CMD_RD_DELAY 0 127 #define LAN9118_MAC_CSR_DATA_RD_DELAY 0 128 #define LAN9118_AFC_CFG_RD_DELAY 0 129 #define LAN9118_E2P_CMD_RD_DELAY 0 130 #define LAN9118_E2P_DATA_RD_DELAY 0 131 132 // Receiver Status bits 133 #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error 134 #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits 135 #define RXSTATUS_MII_ERROR BIT3 // Receive error during interception 136 #define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb 137 #define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame 138 #define RXSTATUS_LCOLL BIT6 // Late collision detected 139 #define RXSTATUS_FTL BIT7 // Frame longer than Ether type 140 #define RXSTATUS_MCF BIT10 // Frame has Multicast Address 141 #define RXSTATUS_RUNT BIT11 // Bad frame 142 #define RXSTATUS_LE BIT12 // Actual length of frame different than it claims 143 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Address 144 #define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11 145 #define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask 146 #define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask 147 #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test 148 149 // Transmitter Status bits 150 #define TXSTATUS_DEF BIT0 // Packet tx was deferred 151 #define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times) 152 #define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask 153 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions) 154 #define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes 155 #define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?) 156 #define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx 157 #define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11 158 #define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for) 159 160 // ID_REV register bits 161 #define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16) 162 #define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF) 163 164 // Interrupt Config Register bits 165 #define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type 166 #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity 167 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 168 #define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line 169 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval 170 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter 171 #define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask 172 173 // Interrupt Status Register bits 174 #define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask 175 #define INSTS_RSFL (0x8) // Rx Status FIFO Level reached 176 #define INSTS_RSFF BIT4 // Rx Status FIFO full 177 #define INSTS_RXDF_INT BIT6 // Rx Frame dropped 178 #define INSTS_TSFL BIT7 // Tx Status FIFO Level reached 179 #define INSTS_TSFF BIT8 // Tx Status FIFO full 180 #define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded 181 #define INSTS_TDFO BIT10 // Tx Data FIFO full 182 #define INSTS_TXE BIT13 // Transmitter Error 183 #define INSTS_RXE BIT14 // Receiver Error 184 #define INSTS_RWT BIT15 // Packet > 2048 bytes received 185 #define INSTS_TXSO BIT16 // Tx Status FIFO Overflow 186 #define INSTS_PME_INT BIT17 // PME Signal detected 187 #define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt 188 #define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF 189 #define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared 190 #define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO 191 #define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF 192 #define INSTS_RXSTOP_INT BIT24 // Rx was stopped 193 #define INSTS_TXSTOP_INT BIT25 // Tx was stopped 194 #define INSTS_SW_INT BIT31 // Software Interrupt occurred 195 196 // Interrupt Enable Register bits 197 198 199 // Hardware Config Register bits 200 #define HWCFG_SRST BIT0 // Software Reset bit (SC) 201 #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO) 202 #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO) 203 #define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size 204 #define HWCFG_MBO BIT20 // Must Be One bit 205 206 // Power Management Control Register 207 #define MPTCTRL_READY BIT0 // Device ready indicator 208 #define MPTCTRL_PME_EN BIT1 // Enable external PME signals 209 #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals 210 #define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec) 211 #define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask 212 #define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull) 213 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 214 #define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan 215 #define MPTCTRL_PHY_RST BIT10 // Reset the PHY 216 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode 217 218 // PHY control register bits 219 #define PHYCR_COLL_TEST BIT7 // Collision test enable 220 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 221 #define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities 222 #define PHYCR_PD BIT11 // Power-Down switch 223 #define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable 224 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection 225 #define PHYCR_LOOPBK BIT14 // Set loopback mode 226 #define PHYCR_RESET BIT15 // Do a PHY reset 227 228 // PHY status register bits 229 #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability 230 #define PHYSTS_JABBER BIT1 // Jabber condition detected 231 #define PHYSTS_LINK_STS BIT2 // Link Status 232 #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability 233 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected 234 #define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed 235 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability 236 #define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability 237 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability 238 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 239 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability 240 241 // PHY Auto-Negotiation advertisement 242 #define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector 243 #define PHYANA_10BASET BIT5 // Advertise 10BASET capability 244 #define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability 245 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability 246 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability 247 #define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability 248 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected 249 250 251 // PHY Auto-Negotiation Link Partner Ability 252 253 // PHY Auto-Negotiation Expansion 254 255 // PHY Mode control/status 256 257 // PHY Special Modes 258 259 // PHY Special control/status 260 261 // PHY Interrupt Source Flags 262 263 // PHY Interrupt Mask 264 265 // PHY Super Special control/status 266 #define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication 267 #define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done 268 269 270 // MAC control register bits 271 #define MACCR_RX_EN BIT2 // Enable Receiver bit 272 #define MACCR_TX_EN BIT3 // Enable Transmitter bit 273 #define MACCR_DFCHK BIT5 // Deferral Check bit 274 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 275 #define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask 276 #define MACCR_DISRTY BIT10 // Disable Transmit Retry bit 277 #define MACCR_BCAST BIT11 // Disable Broadcast Frames bit 278 #define MACCR_LCOLL BIT12 // Late Collision Control bit 279 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit 280 #define MACCR_HO BIT15 // Hash Only Filtering Mode 281 #define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit 282 #define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit 283 #define MACCR_PRMS BIT18 // Promiscuous Mode bit 284 #define MACCR_MCPAS BIT19 // Pass all Multicast packets bit 285 #define MACCR_FDPX BIT20 // Full Duplex Mode bit 286 #define MACCR_LOOPBK BIT21 // Loopback operation mode bit 287 #define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit 288 #define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter 289 290 // Wake-Up Control and Status Register 291 #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P) 292 #define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames 293 #define WUCSR_MPR_MASK (0x10) // Received Magic Packet 294 #define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame 295 #define WUCSR_GUE BIT9 // Enable wake on global unicast frames 296 297 // RX Configuration Register bits 298 #define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes 299 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs 300 #define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO 301 #define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO 302 #define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve 303 304 // TX Configuration Register bits 305 #define TXCFG_STOP_TX BIT0 // Stop the transmitter 306 #define TXCFG_TX_ON BIT1 // Start the transmitter 307 #define TXCFG_TXSAO BIT2 // Tx Status FIFO full 308 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO 309 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO 310 311 // Rx FIFO Information Register bits 312 #define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space 313 #define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space 314 315 // Tx FIFO Information Register bits 316 #define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space 317 #define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space 318 319 // E2P Register 320 #define E2P_EPC_BUSY BIT31 321 #define E2P_EPC_CMD_READ (0) 322 #define E2P_EPC_TIMEOUT BIT9 323 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8 324 #define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF) 325 326 // GPIO Configuration register 327 #define GPIO_GPIO0_PUSH_PULL BIT16 328 #define GPIO_GPIO1_PUSH_PULL BIT17 329 #define GPIO_GPIO2_PUSH_PULL BIT18 330 #define GPIO_LED1_ENABLE BIT28 331 #define GPIO_LED2_ENABLE BIT29 332 #define GPIO_LED3_ENABLE BIT30 333 334 // MII_ACC bits 335 #define MII_ACC_MII_BUSY BIT0 336 #define MII_ACC_MII_WRITE BIT1 337 #define MII_ACC_MII_READ 0 338 339 #define MII_ACC_PHY_VALUE BIT11 340 #define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6) 341 342 // 343 // PHY Control Indexes 344 // 345 #define PHY_INDEX_BASIC_CTRL 0 346 #define PHY_INDEX_BASIC_STATUS 1 347 #define PHY_INDEX_ID1 2 348 #define PHY_INDEX_ID2 3 349 #define PHY_INDEX_AUTO_NEG_ADVERT 4 350 #define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5 351 #define PHY_INDEX_AUTO_NEG_EXP 6 352 #define PHY_INDEX_MODE 17 353 #define PHY_INDEX_SPECIAL_MODES 18 354 #define PHY_INDEX_SPECIAL_CTLR 27 355 #define PHY_INDEX_INT_SRC 29 356 #define PHY_INDEX_INT_MASK 30 357 #define PHY_INDEX_SPECIAL_PHY_CTLR 31 358 359 // Indirect MAC Indexes 360 #define INDIRECT_MAC_INDEX_CR 1 361 #define INDIRECT_MAC_INDEX_ADDRH 2 362 #define INDIRECT_MAC_INDEX_ADDRL 3 363 #define INDIRECT_MAC_INDEX_HASHH 4 364 #define INDIRECT_MAC_INDEX_HASHL 5 365 #define INDIRECT_MAC_INDEX_MII_ACC 6 366 #define INDIRECT_MAC_INDEX_MII_DATA 7 367 368 // 369 // MAC CSR Synchronizer Command register 370 // 371 #define MAC_CSR_BUSY BIT31 372 #define MAC_CSR_READ BIT30 373 #define MAC_CSR_WRITE 0 374 #define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF) 375 376 // 377 // TX Packet Format 378 // 379 #define TX_CMD_A_COMPLETION_INT BIT31 380 #define TX_CMD_A_FIRST_SEGMENT BIT13 381 #define TX_CMD_A_LAST_SEGMENT BIT12 382 #define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF) 383 #define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16) 384 #define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF) 385 #define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16) 386 387 // Hardware Configuration Register 388 #define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16) 389 #define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16) 390 391 // EEPROM Definition 392 #define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5 393 394 // 395 // Conditional compilation flags 396 // 397 //#define EVAL_PERFORMANCE 398 399 400 #endif /* __LAN9118_DXE_HDR_H__ */ 401
