1 /* 2 * PowerPC memory management structures 3 */ 4 5 #ifndef _PPC_MMU_H_ 6 #define _PPC_MMU_H_ 7 8 #ifndef __ASSEMBLY__ 9 /* Hardware Page Table Entry */ 10 typedef struct _PTE { 11 #ifdef CONFIG_PPC64BRIDGE 12 unsigned long long vsid:52; 13 unsigned long api:5; 14 unsigned long :5; 15 unsigned long h:1; 16 unsigned long v:1; 17 unsigned long long rpn:52; 18 #else /* CONFIG_PPC64BRIDGE */ 19 unsigned long v:1; /* Entry is valid */ 20 unsigned long vsid:24; /* Virtual segment identifier */ 21 unsigned long h:1; /* Hash algorithm indicator */ 22 unsigned long api:6; /* Abbreviated page index */ 23 unsigned long rpn:20; /* Real (physical) page number */ 24 #endif /* CONFIG_PPC64BRIDGE */ 25 unsigned long :3; /* Unused */ 26 unsigned long r:1; /* Referenced */ 27 unsigned long c:1; /* Changed */ 28 unsigned long w:1; /* Write-thru cache mode */ 29 unsigned long i:1; /* Cache inhibited */ 30 unsigned long m:1; /* Memory coherence */ 31 unsigned long g:1; /* Guarded */ 32 unsigned long :1; /* Unused */ 33 unsigned long pp:2; /* Page protection */ 34 } PTE; 35 36 /* Values for PP (assumes Ks=0, Kp=1) */ 37 #define PP_RWXX 0 /* Supervisor read/write, User none */ 38 #define PP_RWRX 1 /* Supervisor read/write, User read */ 39 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 40 #define PP_RXRX 3 /* Supervisor read, User read */ 41 42 /* Segment Register */ 43 typedef struct _SEGREG { 44 unsigned long t:1; /* Normal or I/O type */ 45 unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 46 unsigned long kp:1; /* User 'key' (normally 1) */ 47 unsigned long n:1; /* No-execute */ 48 unsigned long :4; /* Unused */ 49 unsigned long vsid:24; /* Virtual Segment Identifier */ 50 } SEGREG; 51 52 /* Block Address Translation (BAT) Registers */ 53 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ 54 unsigned long bepi:15; /* Effective page index (virtual address) */ 55 unsigned long :8; /* unused */ 56 unsigned long w:1; 57 unsigned long i:1; /* Cache inhibit */ 58 unsigned long m:1; /* Memory coherence */ 59 unsigned long ks:1; /* Supervisor key (normally 0) */ 60 unsigned long kp:1; /* User key (normally 1) */ 61 unsigned long pp:2; /* Page access protections */ 62 } P601_BATU; 63 64 typedef struct _BATU { /* Upper part of BAT (all except 601) */ 65 #ifdef CONFIG_PPC64BRIDGE 66 unsigned long long bepi:47; 67 #else /* CONFIG_PPC64BRIDGE */ 68 unsigned long bepi:15; /* Effective page index (virtual address) */ 69 #endif /* CONFIG_PPC64BRIDGE */ 70 unsigned long :4; /* Unused */ 71 unsigned long bl:11; /* Block size mask */ 72 unsigned long vs:1; /* Supervisor valid */ 73 unsigned long vp:1; /* User valid */ 74 } BATU; 75 76 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ 77 unsigned long brpn:15; /* Real page index (physical address) */ 78 unsigned long :10; /* Unused */ 79 unsigned long v:1; /* Valid bit */ 80 unsigned long bl:6; /* Block size mask */ 81 } P601_BATL; 82 83 typedef struct _BATL { /* Lower part of BAT (all except 601) */ 84 #ifdef CONFIG_PPC64BRIDGE 85 unsigned long long brpn:47; 86 #else /* CONFIG_PPC64BRIDGE */ 87 unsigned long brpn:15; /* Real page index (physical address) */ 88 #endif /* CONFIG_PPC64BRIDGE */ 89 unsigned long :10; /* Unused */ 90 unsigned long w:1; /* Write-thru cache */ 91 unsigned long i:1; /* Cache inhibit */ 92 unsigned long m:1; /* Memory coherence */ 93 unsigned long g:1; /* Guarded (MBZ in IBAT) */ 94 unsigned long :1; /* Unused */ 95 unsigned long pp:2; /* Page access protections */ 96 } BATL; 97 98 typedef struct _BAT { 99 BATU batu; /* Upper register */ 100 BATL batl; /* Lower register */ 101 } BAT; 102 103 typedef struct _P601_BAT { 104 P601_BATU batu; /* Upper register */ 105 P601_BATL batl; /* Lower register */ 106 } P601_BAT; 107 108 /* 109 * Simulated two-level MMU. This structure is used by the kernel 110 * to keep track of MMU mappings and is used to update/maintain 111 * the hardware HASH table which is really a cache of mappings. 112 * 113 * The simulated structures mimic the hardware available on other 114 * platforms, notably the 80x86 and 680x0. 115 */ 116 117 typedef struct _pte { 118 unsigned long page_num:20; 119 unsigned long flags:12; /* Page flags (some unused bits) */ 120 } pte; 121 122 #define PD_SHIFT (10+12) /* Page directory */ 123 #define PD_MASK 0x02FF 124 #define PT_SHIFT (12) /* Page Table */ 125 #define PT_MASK 0x02FF 126 #define PG_SHIFT (12) /* Page Entry */ 127 128 129 /* MMU context */ 130 131 typedef struct _MMU_context { 132 SEGREG segs[16]; /* Segment registers */ 133 pte **pmap; /* Two-level page-map structure */ 134 } MMU_context; 135 136 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 137 extern void _tlbia(void); /* invalidate all TLB entries */ 138 139 #ifdef CONFIG_ADDR_MAP 140 extern void init_addr_map(void); 141 #endif 142 143 typedef enum { 144 IBAT0 = 0, IBAT1, IBAT2, IBAT3, 145 DBAT0, DBAT1, DBAT2, DBAT3, 146 #ifdef CONFIG_HIGH_BATS 147 IBAT4, IBAT5, IBAT6, IBAT7, 148 DBAT4, DBAT5, DBAT6, DBAT7 149 #endif 150 } ppc_bat_t; 151 152 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); 153 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); 154 extern void print_bats(void); 155 156 #endif /* __ASSEMBLY__ */ 157 158 #define BATU_VS 0x00000002 159 #define BATU_VP 0x00000001 160 #define BATU_INVALID 0x00000000 161 162 #define BATL_WRITETHROUGH 0x00000040 163 #define BATL_CACHEINHIBIT 0x00000020 164 #define BATL_MEMCOHERENCE 0x00000010 165 #define BATL_GUARDEDSTORAGE 0x00000008 166 #define BATL_NO_ACCESS 0x00000000 167 168 #define BATL_PP_MSK 0x00000003 169 #define BATL_PP_00 0x00000000 /* No access */ 170 #define BATL_PP_01 0x00000001 /* Read-only */ 171 #define BATL_PP_10 0x00000002 /* Read-write */ 172 #define BATL_PP_11 0x00000003 173 174 #define BATL_PP_NO_ACCESS BATL_PP_00 175 #define BATL_PP_RO BATL_PP_01 176 #define BATL_PP_RW BATL_PP_10 177 178 /* BAT Block size values */ 179 #define BATU_BL_128K 0x00000000 180 #define BATU_BL_256K 0x00000004 181 #define BATU_BL_512K 0x0000000c 182 #define BATU_BL_1M 0x0000001c 183 #define BATU_BL_2M 0x0000003c 184 #define BATU_BL_4M 0x0000007c 185 #define BATU_BL_8M 0x000000fc 186 #define BATU_BL_16M 0x000001fc 187 #define BATU_BL_32M 0x000003fc 188 #define BATU_BL_64M 0x000007fc 189 #define BATU_BL_128M 0x00000ffc 190 #define BATU_BL_256M 0x00001ffc 191 192 /* Block lengths for processors that support extended block length */ 193 #ifdef HID0_XBSEN 194 #define BATU_BL_512M 0x00003ffc 195 #define BATU_BL_1G 0x00007ffc 196 #define BATU_BL_2G 0x0000fffc 197 #define BATU_BL_4G 0x0001fffc 198 #define BATU_BL_MAX BATU_BL_4G 199 #else 200 #define BATU_BL_MAX BATU_BL_256M 201 #endif 202 203 /* BAT Access Protection */ 204 #define BPP_XX 0x00 /* No access */ 205 #define BPP_RX 0x01 /* Read only */ 206 #define BPP_RW 0x02 /* Read/write */ 207 208 /* Macros to get values from BATs, once data is in the BAT register format */ 209 #define BATU_VALID(x) (x & 0x3) 210 #define BATU_VADDR(x) (x & 0xfffe0000) 211 #define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ 212 | ((x & 0x0e00ULL) << 24) \ 213 | ((x & 0x04ULL) << 30))) 214 #define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17)) 215 216 /* bytes into BATU_BL */ 217 #define TO_BATU_BL(x) \ 218 (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4) 219 220 /* Used to set up SDR1 register */ 221 #define HASH_TABLE_SIZE_64K 0x00010000 222 #define HASH_TABLE_SIZE_128K 0x00020000 223 #define HASH_TABLE_SIZE_256K 0x00040000 224 #define HASH_TABLE_SIZE_512K 0x00080000 225 #define HASH_TABLE_SIZE_1M 0x00100000 226 #define HASH_TABLE_SIZE_2M 0x00200000 227 #define HASH_TABLE_SIZE_4M 0x00400000 228 #define HASH_TABLE_MASK_64K 0x000 229 #define HASH_TABLE_MASK_128K 0x001 230 #define HASH_TABLE_MASK_256K 0x003 231 #define HASH_TABLE_MASK_512K 0x007 232 #define HASH_TABLE_MASK_1M 0x00F 233 #define HASH_TABLE_MASK_2M 0x01F 234 #define HASH_TABLE_MASK_4M 0x03F 235 236 /* Control/status registers for the MPC8xx. 237 * A write operation to these registers causes serialized access. 238 * During software tablewalk, the registers used perform mask/shift-add 239 * operations when written/read. A TLB entry is created when the Mx_RPN 240 * is written, and the contents of several registers are used to 241 * create the entry. 242 */ 243 #define MI_CTR 784 /* Instruction TLB control register */ 244 #define MI_GPM 0x80000000 /* Set domain manager mode */ 245 #define MI_PPM 0x40000000 /* Set subpage protection */ 246 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 247 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 248 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 249 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ 250 #define MI_RESETVAL 0x00000000 /* Value of register at reset */ 251 252 /* These are the Ks and Kp from the PowerPC books. For proper operation, 253 * Ks = 0, Kp = 1. 254 */ 255 #define MI_AP 786 256 #define MI_Ks 0x80000000 /* Should not be set */ 257 #define MI_Kp 0x40000000 /* Should always be set */ 258 259 /* The effective page number register. When read, contains the information 260 * about the last instruction TLB miss. When MI_RPN is written, bits in 261 * this register are used to create the TLB entry. 262 */ 263 #define MI_EPN 787 264 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ 265 #define MI_EVALID 0x00000200 /* Entry is valid */ 266 #define MI_ASIDMASK 0x0000000f /* ASID match value */ 267 /* Reset value is undefined */ 268 269 /* A "level 1" or "segment" or whatever you want to call it register. 270 * For the instruction TLB, it contains bits that get loaded into the 271 * TLB entry when the MI_RPN is written. 272 */ 273 #define MI_TWC 789 274 #define MI_APG 0x000001e0 /* Access protection group (0) */ 275 #define MI_GUARDED 0x00000010 /* Guarded storage */ 276 #define MI_PSMASK 0x0000000c /* Mask of page size bits */ 277 #define MI_PS8MEG 0x0000000c /* 8M page size */ 278 #define MI_PS512K 0x00000004 /* 512K page size */ 279 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ 280 #define MI_SVALID 0x00000001 /* Segment entry is valid */ 281 /* Reset value is undefined */ 282 283 /* Real page number. Defined by the pte. Writing this register 284 * causes a TLB entry to be created for the instruction TLB, using 285 * additional information from the MI_EPN, and MI_TWC registers. 286 */ 287 #define MI_RPN 790 288 289 /* Define an RPN value for mapping kernel memory to large virtual 290 * pages for boot initialization. This has real page number of 0, 291 * large page size, shared page, cache enabled, and valid. 292 * Also mark all subpages valid and write access. 293 */ 294 #define MI_BOOTINIT 0x000001fd 295 296 #define MD_CTR 792 /* Data TLB control register */ 297 #define MD_GPM 0x80000000 /* Set domain manager mode */ 298 #define MD_PPM 0x40000000 /* Set subpage protection */ 299 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 300 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ 301 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 302 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ 303 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 304 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ 305 #define MD_RESETVAL 0x04000000 /* Value of register at reset */ 306 307 #define M_CASID 793 /* Address space ID (context) to match */ 308 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ 309 310 311 /* These are the Ks and Kp from the PowerPC books. For proper operation, 312 * Ks = 0, Kp = 1. 313 */ 314 #define MD_AP 794 315 #define MD_Ks 0x80000000 /* Should not be set */ 316 #define MD_Kp 0x40000000 /* Should always be set */ 317 318 /* The effective page number register. When read, contains the information 319 * about the last instruction TLB miss. When MD_RPN is written, bits in 320 * this register are used to create the TLB entry. 321 */ 322 #define MD_EPN 795 323 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ 324 #define MD_EVALID 0x00000200 /* Entry is valid */ 325 #define MD_ASIDMASK 0x0000000f /* ASID match value */ 326 /* Reset value is undefined */ 327 328 /* The pointer to the base address of the first level page table. 329 * During a software tablewalk, reading this register provides the address 330 * of the entry associated with MD_EPN. 331 */ 332 #define M_TWB 796 333 #define M_L1TB 0xfffff000 /* Level 1 table base address */ 334 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ 335 /* Reset value is undefined */ 336 337 /* A "level 1" or "segment" or whatever you want to call it register. 338 * For the data TLB, it contains bits that get loaded into the TLB entry 339 * when the MD_RPN is written. It is also provides the hardware assist 340 * for finding the PTE address during software tablewalk. 341 */ 342 #define MD_TWC 797 343 #define MD_L2TB 0xfffff000 /* Level 2 table base address */ 344 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ 345 #define MD_APG 0x000001e0 /* Access protection group (0) */ 346 #define MD_GUARDED 0x00000010 /* Guarded storage */ 347 #define MD_PSMASK 0x0000000c /* Mask of page size bits */ 348 #define MD_PS8MEG 0x0000000c /* 8M page size */ 349 #define MD_PS512K 0x00000004 /* 512K page size */ 350 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ 351 #define MD_WT 0x00000002 /* Use writethrough page attribute */ 352 #define MD_SVALID 0x00000001 /* Segment entry is valid */ 353 /* Reset value is undefined */ 354 355 356 /* Real page number. Defined by the pte. Writing this register 357 * causes a TLB entry to be created for the data TLB, using 358 * additional information from the MD_EPN, and MD_TWC registers. 359 */ 360 #define MD_RPN 798 361 362 /* This is a temporary storage register that could be used to save 363 * a processor working register during a tablewalk. 364 */ 365 #define M_TW 799 366 367 /* 368 * At present, all PowerPC 400-class processors share a similar TLB 369 * architecture. The instruction and data sides share a unified, 370 * 64-entry, fully-associative TLB which is maintained totally under 371 * software control. In addition, the instruction side has a 372 * hardware-managed, 4-entry, fully- associative TLB which serves as a 373 * first level to the shared TLB. These two TLBs are known as the UTLB 374 * and ITLB, respectively. 375 */ 376 377 #define PPC4XX_TLB_SIZE 64 378 379 /* 380 * TLB entries are defined by a "high" tag portion and a "low" data 381 * portion. On all architectures, the data portion is 32-bits. 382 * 383 * TLB entries are managed entirely under software control by reading, 384 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx 385 * instructions. 386 */ 387 388 /* 389 * FSL Book-E support 390 */ 391 392 #define MAS0_TLBSEL_MSK 0x30000000 393 #define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) 394 #define MAS0_ESEL_MSK 0x0FFF0000 395 #define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) 396 #define MAS0_NV(x) ((x) & 0x00000FFF) 397 398 #define MAS1_VALID 0x80000000 399 #define MAS1_IPROT 0x40000000 400 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) 401 #define MAS1_TS 0x00001000 402 #define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80) 403 #define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10)) 404 405 #define MAS2_EPN 0xFFFFF000 406 #define MAS2_X0 0x00000040 407 #define MAS2_X1 0x00000020 408 #define MAS2_W 0x00000010 409 #define MAS2_I 0x00000008 410 #define MAS2_M 0x00000004 411 #define MAS2_G 0x00000002 412 #define MAS2_E 0x00000001 413 414 #define MAS3_RPN 0xFFFFF000 415 #define MAS3_U0 0x00000200 416 #define MAS3_U1 0x00000100 417 #define MAS3_U2 0x00000080 418 #define MAS3_U3 0x00000040 419 #define MAS3_UX 0x00000020 420 #define MAS3_SX 0x00000010 421 #define MAS3_UW 0x00000008 422 #define MAS3_SW 0x00000004 423 #define MAS3_UR 0x00000002 424 #define MAS3_SR 0x00000001 425 426 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) 427 #define MAS4_TIDDSEL 0x000F0000 428 #define MAS4_TSIZED(x) MAS1_TSIZE(x) 429 #define MAS4_X0D 0x00000040 430 #define MAS4_X1D 0x00000020 431 #define MAS4_WD 0x00000010 432 #define MAS4_ID 0x00000008 433 #define MAS4_MD 0x00000004 434 #define MAS4_GD 0x00000002 435 #define MAS4_ED 0x00000001 436 437 #define MAS6_SPID0 0x3FFF0000 438 #define MAS6_SPID1 0x00007FFE 439 #define MAS6_SAS 0x00000001 440 #define MAS6_SPID MAS6_SPID0 441 442 #define MAS7_RPN 0xFFFFFFFF 443 444 #define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ 445 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) 446 #define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ 447 ((((v) << 31) & MAS1_VALID) |\ 448 (((iprot) << 30) & MAS1_IPROT) |\ 449 (MAS1_TID(tid)) |\ 450 (((ts) << 12) & MAS1_TS) |\ 451 (MAS1_TSIZE(tsize))) 452 #define FSL_BOOKE_MAS2(epn, wimge) \ 453 (((epn) & MAS3_RPN) | (wimge)) 454 #define FSL_BOOKE_MAS3(rpn, user, perms) \ 455 (((rpn) & MAS3_RPN) | (user) | (perms)) 456 #define FSL_BOOKE_MAS7(rpn) \ 457 (((u64)(rpn)) >> 32) 458 459 #define BOOKE_PAGESZ_1K 0 460 #define BOOKE_PAGESZ_2K 1 461 #define BOOKE_PAGESZ_4K 2 462 #define BOOKE_PAGESZ_8K 3 463 #define BOOKE_PAGESZ_16K 4 464 #define BOOKE_PAGESZ_32K 5 465 #define BOOKE_PAGESZ_64K 6 466 #define BOOKE_PAGESZ_128K 7 467 #define BOOKE_PAGESZ_256K 8 468 #define BOOKE_PAGESZ_512K 9 469 #define BOOKE_PAGESZ_1M 10 470 #define BOOKE_PAGESZ_2M 11 471 #define BOOKE_PAGESZ_4M 12 472 #define BOOKE_PAGESZ_8M 13 473 #define BOOKE_PAGESZ_16M 14 474 #define BOOKE_PAGESZ_32M 15 475 #define BOOKE_PAGESZ_64M 16 476 #define BOOKE_PAGESZ_128M 17 477 #define BOOKE_PAGESZ_256M 18 478 #define BOOKE_PAGESZ_512M 19 479 #define BOOKE_PAGESZ_1G 20 480 #define BOOKE_PAGESZ_2G 21 481 #define BOOKE_PAGESZ_4G 22 482 #define BOOKE_PAGESZ_8G 23 483 #define BOOKE_PAGESZ_16GB 24 484 #define BOOKE_PAGESZ_32GB 25 485 #define BOOKE_PAGESZ_64GB 26 486 #define BOOKE_PAGESZ_128GB 27 487 #define BOOKE_PAGESZ_256GB 28 488 #define BOOKE_PAGESZ_512GB 29 489 #define BOOKE_PAGESZ_1TB 30 490 #define BOOKE_PAGESZ_2TB 31 491 492 #define TLBIVAX_ALL 4 493 #define TLBIVAX_TLB0 0 494 #define TLBIVAX_TLB1 8 495 496 #ifdef CONFIG_E500 497 #ifndef __ASSEMBLY__ 498 extern void set_tlb(u8 tlb, u32 epn, u64 rpn, 499 u8 perms, u8 wimge, 500 u8 ts, u8 esel, u8 tsize, u8 iprot); 501 extern void disable_tlb(u8 esel); 502 extern void invalidate_tlb(u8 tlb); 503 extern void init_tlbs(void); 504 extern int find_tlb_idx(void *addr, u8 tlbsel); 505 extern void init_used_tlb_cams(void); 506 extern int find_free_tlbcam(void); 507 extern void print_tlbcam(void); 508 509 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); 510 extern void clear_ddr_tlbs(unsigned int memsize_in_meg); 511 512 enum tlb_map_type { 513 TLB_MAP_RAM, 514 TLB_MAP_IO, 515 }; 516 517 extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, 518 enum tlb_map_type map_type); 519 520 extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); 521 522 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ 523 { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ 524 .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ 525 .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ 526 .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ 527 .mas7 = FSL_BOOKE_MAS7(_rpn), } 528 529 struct fsl_e_tlb_entry { 530 u32 mas0; 531 u32 mas1; 532 u32 mas2; 533 u32 mas3; 534 u32 mas7; 535 }; 536 537 extern struct fsl_e_tlb_entry tlb_table[]; 538 extern int num_tlb_entries; 539 #endif 540 #endif 541 542 #ifdef CONFIG_E300 543 #define LAWAR_EN 0x80000000 544 #define LAWAR_SIZE 0x0000003F 545 546 #define LAWAR_TRGT_IF_PCI 0x00000000 547 #define LAWAR_TRGT_IF_PCI1 0x00000000 548 #define LAWAR_TRGT_IF_PCIX 0x00000000 549 #define LAWAR_TRGT_IF_PCI2 0x00100000 550 #define LAWAR_TRGT_IF_PCIE1 0x00200000 551 #define LAWAR_TRGT_IF_PCIE2 0x00100000 552 #define LAWAR_TRGT_IF_PCIE3 0x00300000 553 #define LAWAR_TRGT_IF_LBC 0x00400000 554 #define LAWAR_TRGT_IF_CCSR 0x00800000 555 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 556 #define LAWAR_TRGT_IF_RIO 0x00c00000 557 #define LAWAR_TRGT_IF_DDR 0x00f00000 558 #define LAWAR_TRGT_IF_DDR1 0x00f00000 559 #define LAWAR_TRGT_IF_DDR2 0x01600000 560 561 #define LAWAR_SIZE_BASE 0xa 562 #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) 563 #define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) 564 #define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) 565 #define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) 566 #define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) 567 #define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) 568 #define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) 569 #define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) 570 #define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) 571 #define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) 572 #define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) 573 #define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) 574 #define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) 575 #define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) 576 #define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) 577 #define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) 578 #define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) 579 #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) 580 #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) 581 #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) 582 #define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) 583 #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) 584 #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) 585 #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) 586 #endif 587 588 #endif /* _PPC_MMU_H_ */ 589
