1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2008-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef _FSL_LAW_H_ 7 #define _FSL_LAW_H_ 8 9 #include <asm/io.h> 10 #include <linux/log2.h> 11 12 #define LAW_EN 0x80000000 13 14 #define SET_LAW_ENTRY(idx, a, sz, trgt) \ 15 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } 16 17 #define SET_LAW(a, sz, trgt) \ 18 { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } 19 20 enum law_size { 21 LAW_SIZE_4K = 0xb, 22 LAW_SIZE_8K, 23 LAW_SIZE_16K, 24 LAW_SIZE_32K, 25 LAW_SIZE_64K, 26 LAW_SIZE_128K, 27 LAW_SIZE_256K, 28 LAW_SIZE_512K, 29 LAW_SIZE_1M, 30 LAW_SIZE_2M, 31 LAW_SIZE_4M, 32 LAW_SIZE_8M, 33 LAW_SIZE_16M, 34 LAW_SIZE_32M, 35 LAW_SIZE_64M, 36 LAW_SIZE_128M, 37 LAW_SIZE_256M, 38 LAW_SIZE_512M, 39 LAW_SIZE_1G, 40 LAW_SIZE_2G, 41 LAW_SIZE_4G, 42 LAW_SIZE_8G, 43 LAW_SIZE_16G, 44 LAW_SIZE_32G, 45 }; 46 47 #define law_size_bits(sz) (__ilog2_u64(sz) - 1) 48 #define lawar_size(x) (1ULL << ((x & 0x3f) + 1)) 49 50 #ifdef CONFIG_FSL_CORENET 51 enum law_trgt_if { 52 LAW_TRGT_IF_PCIE_1 = 0x00, 53 LAW_TRGT_IF_PCIE_2 = 0x01, 54 LAW_TRGT_IF_PCIE_3 = 0x02, 55 LAW_TRGT_IF_PCIE_4 = 0x03, 56 LAW_TRGT_IF_RIO_1 = 0x08, 57 LAW_TRGT_IF_RIO_2 = 0x09, 58 59 LAW_TRGT_IF_DDR_1 = 0x10, 60 LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ 61 LAW_TRGT_IF_DDR_3 = 0x12, 62 LAW_TRGT_IF_DDR_4 = 0x13, 63 LAW_TRGT_IF_DDR_INTRLV = 0x14, 64 LAW_TRGT_IF_DDR_INTLV_34 = 0x15, 65 LAW_TRGT_IF_DDR_INTLV_123 = 0x17, 66 LAW_TRGT_IF_DDR_INTLV_1234 = 0x16, 67 LAW_TRGT_IF_BMAN = 0x18, 68 LAW_TRGT_IF_DCSR = 0x1d, 69 LAW_TRGT_IF_CCSR = 0x1e, 70 LAW_TRGT_IF_LBC = 0x1f, 71 LAW_TRGT_IF_QMAN = 0x3c, 72 73 LAW_TRGT_IF_MAPLE = 0x50, 74 }; 75 #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 76 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC 77 #else 78 enum law_trgt_if { 79 LAW_TRGT_IF_PCI = 0x00, 80 LAW_TRGT_IF_PCI_2 = 0x01, 81 #ifndef CONFIG_ARCH_MPC8641 82 LAW_TRGT_IF_PCIE_1 = 0x02, 83 #endif 84 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) 85 LAW_TRGT_IF_OCN_DSP = 0x03, 86 #else 87 #if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020) 88 LAW_TRGT_IF_PCIE_3 = 0x03, 89 #endif 90 #endif 91 LAW_TRGT_IF_LBC = 0x04, 92 LAW_TRGT_IF_CCSR = 0x08, 93 LAW_TRGT_IF_DSP_CCSR = 0x09, 94 LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, 95 LAW_TRGT_IF_DDR_INTRLV = 0x0b, 96 LAW_TRGT_IF_RIO = 0x0c, 97 #if defined(CONFIG_ARCH_BSC9132) 98 LAW_TRGT_IF_CLASS_DSP = 0x0d, 99 #else 100 LAW_TRGT_IF_RIO_2 = 0x0d, 101 #endif 102 LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, 103 LAW_TRGT_IF_DDR = 0x0f, 104 LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ 105 /* place holder for 3-way and 4-way interleaving */ 106 LAW_TRGT_IF_DDR_3, 107 LAW_TRGT_IF_DDR_4, 108 LAW_TRGT_IF_DDR_INTLV_34, 109 LAW_TRGT_IF_DDR_INTLV_123, 110 LAW_TRGT_IF_DDR_INTLV_1234, 111 }; 112 #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR 113 #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI 114 #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI 115 #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 116 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO 117 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC 118 119 #ifdef CONFIG_ARCH_MPC8641 120 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI 121 #endif 122 123 #if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) 124 #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI 125 #endif 126 #endif /* CONFIG_FSL_CORENET */ 127 128 struct law_entry { 129 int index; 130 phys_addr_t addr; 131 enum law_size size; 132 enum law_trgt_if trgt_id; 133 }; 134 135 extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 136 extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 137 extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 138 extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); 139 extern struct law_entry find_law(phys_addr_t addr); 140 extern void disable_law(u8 idx); 141 extern void init_laws(void); 142 extern void print_laws(void); 143 144 /* define in board code */ 145 extern struct law_entry law_table[]; 146 extern int num_law_entries; 147 #endif 148
