1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla (at) marvell.com> 6 * 7 * Header file for the Marvell's Feroceon CPU core. 8 */ 9 10 #ifndef _MVEBU_SOC_H 11 #define _MVEBU_SOC_H 12 13 #define SOC_MV78230_ID 0x7823 14 #define SOC_MV78260_ID 0x7826 15 #define SOC_MV78460_ID 0x7846 16 #define SOC_88F6720_ID 0x6720 17 #define SOC_88F6810_ID 0x6810 18 #define SOC_88F6820_ID 0x6820 19 #define SOC_88F6828_ID 0x6828 20 #define SOC_98DX3236_ID 0xf410 21 #define SOC_98DX3336_ID 0xf400 22 #define SOC_98DX4251_ID 0xfc00 23 24 /* A375 revisions */ 25 #define MV_88F67XX_A0_ID 0x3 26 27 /* A38x revisions */ 28 #define MV_88F68XX_Z1_ID 0x0 29 #define MV_88F68XX_A0_ID 0x4 30 31 /* TCLK Core Clock definition */ 32 #ifndef CONFIG_SYS_TCLK 33 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 34 #endif 35 36 /* SOC specific definations */ 37 #define INTREG_BASE 0xd0000000 38 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) 39 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700) 40 /* 41 * The SPL U-Boot version still runs with the default 42 * address for the internal registers, configured by 43 * the BootROM. Only the main U-Boot version uses the 44 * new internal register base address, that also is 45 * required for the Linux kernel. 46 */ 47 #define SOC_REGS_PHY_BASE 0xd0000000 48 #elif defined(CONFIG_ARMADA_8K) 49 #define SOC_REGS_PHY_BASE 0xf0000000 50 #else 51 #define SOC_REGS_PHY_BASE 0xf1000000 52 #endif 53 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) 54 55 #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) 56 #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) 57 #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE 58 #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) 59 #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) 60 #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) 61 #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) 62 #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) 63 #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) 64 #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) 65 #define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700)) 66 #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) 67 #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) 68 #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) 69 #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) 70 #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) 71 #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) 72 #define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000)) 73 #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) 74 #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) 75 #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) 76 #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) 77 #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) 78 #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) 79 80 #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) 81 #define MBUS_ERR_PROP_EN (1 << 8) 82 83 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250)) 84 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254)) 85 86 #define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08) 87 #define NAND_EN BIT(0) 88 #define NAND_ARBITER_EN BIT(27) 89 90 #define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c) 91 #define GE0_PUP_EN BIT(0) 92 #define GE1_PUP_EN BIT(1) 93 #define LCD_PUP_EN BIT(2) 94 #define NAND_PUP_EN BIT(4) 95 #define SPI_PUP_EN BIT(5) 96 97 #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) 98 #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) 99 #define NAND_ECC_DIVCKL_RATIO_OFFS 8 100 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) 101 102 #define SDRAM_MAX_CS 4 103 #define SDRAM_ADDR_MASK 0xFF000000 104 105 /* MVEBU CPU memory windows */ 106 #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA 107 #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE 108 #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE 109 110 #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) 111 112 /* BootROM error register (also includes some status infos) */ 113 #if defined(CONFIG_ARMADA_38X) 114 #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) 115 #define BOOTROM_ERR_MODE_OFFS 0 116 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) 117 #else 118 #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) 119 #define BOOTROM_ERR_MODE_OFFS 28 120 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) 121 #define BOOTROM_ERR_MODE_UART 0x6 122 #endif 123 124 #if defined(CONFIG_ARMADA_375) 125 /* SAR values for Armada 375 */ 126 #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) 127 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204)) 128 129 #define SAR_CPU_FREQ_OFFS 17 130 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 131 132 #define BOOT_DEV_SEL_OFFS 3 133 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 134 135 #define BOOT_FROM_UART 0x30 136 #define BOOT_FROM_SPI 0x38 137 #elif defined(CONFIG_ARMADA_38X) 138 /* SAR values for Armada 38x */ 139 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) 140 141 #define SAR_CPU_FREQ_OFFS 10 142 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 143 #define SAR_BOOT_DEVICE_OFFS 4 144 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) 145 146 #define BOOT_DEV_SEL_OFFS 4 147 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 148 149 #define BOOT_FROM_NAND 0x0A 150 #define BOOT_FROM_UART 0x28 151 #define BOOT_FROM_UART_ALT 0x3f 152 #define BOOT_FROM_SPI 0x32 153 #define BOOT_FROM_MMC 0x30 154 #define BOOT_FROM_MMC_ALT 0x31 155 #else 156 /* SAR values for Armada XP */ 157 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) 158 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) 159 160 #define SAR_CPU_FREQ_OFFS 21 161 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 162 #define SAR_FFC_FREQ_OFFS 24 163 #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) 164 #define SAR2_CPU_FREQ_OFFS 20 165 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) 166 #define SAR_BOOT_DEVICE_OFFS 5 167 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) 168 169 #define BOOT_DEV_SEL_OFFS 5 170 #define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) 171 172 #define BOOT_FROM_UART 0x2 173 #define BOOT_FROM_SPI 0x3 174 #endif 175 176 #endif /* _MVEBU_SOC_H */ 177
