1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __JUNO_DEF_H__ 8 #define __JUNO_DEF_H__ 9 10 11 /******************************************************************************* 12 * Juno memory map related constants 13 ******************************************************************************/ 14 15 /* Board revisions */ 16 #define REV_JUNO_R0 0x1 /* Rev B */ 17 #define REV_JUNO_R1 0x2 /* Rev C */ 18 #define REV_JUNO_R2 0x3 /* Rev D */ 19 20 /* Bypass offset from start of NOR flash */ 21 #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 22 23 #define EMMC_BASE 0x0c000000 24 #define EMMC_SIZE 0x04000000 25 26 #define PSRAM_BASE 0x14000000 27 #define PSRAM_SIZE 0x02000000 28 29 #define JUNO_SSC_VER_PART_NUM 0x030 30 31 /******************************************************************************* 32 * Juno topology related constants 33 ******************************************************************************/ 34 #define JUNO_CLUSTER_COUNT 2 35 #define JUNO_CLUSTER0_CORE_COUNT 2 36 #define JUNO_CLUSTER1_CORE_COUNT 4 37 38 /******************************************************************************* 39 * TZC-400 related constants 40 ******************************************************************************/ 41 #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 42 #define TZC400_NSAID_PCIE 1 43 #define TZC400_NSAID_HDLCD0 2 44 #define TZC400_NSAID_HDLCD1 3 45 #define TZC400_NSAID_USB 4 46 #define TZC400_NSAID_DMA330 5 47 #define TZC400_NSAID_THINLINKS 6 48 #define TZC400_NSAID_AP 9 49 #define TZC400_NSAID_GPU 10 50 #define TZC400_NSAID_SCP 11 51 #define TZC400_NSAID_CORESIGHT 12 52 53 /******************************************************************************* 54 * TRNG related constants 55 ******************************************************************************/ 56 #define TRNG_BASE 0x7FE60000ULL 57 #define TRNG_NOUTPUTS 4 58 #define TRNG_STATUS 0x10 59 #define TRNG_INTMASK 0x14 60 #define TRNG_CONFIG 0x18 61 #define TRNG_CONTROL 0x1C 62 #define TRNG_NBYTES 16 /* Number of bytes generated per round. */ 63 64 /******************************************************************************* 65 * MMU-401 related constants 66 ******************************************************************************/ 67 #define MMU401_SSD_OFFSET 0x4000 68 #define MMU401_DMA330_BASE 0x7fb00000 69 70 /******************************************************************************* 71 * Interrupt handling constants 72 ******************************************************************************/ 73 #define JUNO_IRQ_DMA_SMMU 126 74 #define JUNO_IRQ_HDLCD0_SMMU 128 75 #define JUNO_IRQ_HDLCD1_SMMU 130 76 #define JUNO_IRQ_USB_SMMU 132 77 #define JUNO_IRQ_THIN_LINKS_SMMU 134 78 #define JUNO_IRQ_SEC_I2C 137 79 #define JUNO_IRQ_GPU_SMMU_1 73 80 #define JUNO_IRQ_ETR_SMMU 75 81 82 #endif /* __JUNO_DEF_H__ */ 83
