1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Linaro 4 * Peter Griffin <peter.griffin (at) linaro.org> 5 */ 6 7 #ifndef __ASM_ARM_ARCH_PINMUX_H 8 #define __ASM_ARM_ARCH_PINMUX_H 9 10 #include "periph.h" 11 12 13 /* iomg bit definition */ 14 #define MUX_M0 0 15 #define MUX_M1 1 16 #define MUX_M2 2 17 #define MUX_M3 3 18 #define MUX_M4 4 19 #define MUX_M5 5 20 #define MUX_M6 6 21 #define MUX_M7 7 22 23 /* iocg bit definition */ 24 #define PULL_MASK (3) 25 #define PULL_DIS (0) 26 #define PULL_UP (1 << 0) 27 #define PULL_DOWN (1 << 1) 28 29 /* drive strength definition */ 30 #define DRIVE_MASK (7 << 4) 31 #define DRIVE1_02MA (0 << 4) 32 #define DRIVE1_04MA (1 << 4) 33 #define DRIVE1_08MA (2 << 4) 34 #define DRIVE1_10MA (3 << 4) 35 #define DRIVE2_02MA (0 << 4) 36 #define DRIVE2_04MA (1 << 4) 37 #define DRIVE2_08MA (2 << 4) 38 #define DRIVE2_10MA (3 << 4) 39 #define DRIVE3_04MA (0 << 4) 40 #define DRIVE3_08MA (1 << 4) 41 #define DRIVE3_12MA (2 << 4) 42 #define DRIVE3_16MA (3 << 4) 43 #define DRIVE3_20MA (4 << 4) 44 #define DRIVE3_24MA (5 << 4) 45 #define DRIVE3_32MA (6 << 4) 46 #define DRIVE3_40MA (7 << 4) 47 #define DRIVE4_02MA (0 << 4) 48 #define DRIVE4_04MA (2 << 4) 49 #define DRIVE4_08MA (4 << 4) 50 #define DRIVE4_10MA (6 << 4) 51 52 #define HI6220_PINMUX0_BASE 0xf7010000 53 #define HI6220_PINMUX1_BASE 0xf7010800 54 55 #ifndef __ASSEMBLY__ 56 57 /* maybe more registers, but highest used is 123 */ 58 #define REG_NUM 123 59 60 struct hi6220_pinmux0_regs { 61 uint32_t iomg[REG_NUM]; 62 }; 63 64 struct hi6220_pinmux1_regs { 65 uint32_t iocfg[REG_NUM]; 66 }; 67 68 #endif 69 70 /** 71 * Configures the pinmux for a particular peripheral. 72 * 73 * This function will configure the peripheral pinmux along with 74 * pull-up/down and drive strength. 75 * 76 * @param peripheral peripheral to be configured 77 * @return 0 if ok, -1 on error (e.g. unsupported peripheral) 78 */ 79 int hi6220_pinmux_config(int peripheral); 80 81 #endif 82
