1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_PBS_H_ 7 #define _DDR3_TRAINING_IP_PBS_H_ 8 9 enum { 10 EBA_CONFIG, 11 EEBA_CONFIG, 12 SBA_CONFIG 13 }; 14 15 enum hws_training_load_op { 16 TRAINING_LOAD_OPERATION_UNLOAD, 17 TRAINING_LOAD_OPERATION_LOAD 18 }; 19 20 enum hws_edge { 21 TRAINING_EDGE_1, 22 TRAINING_EDGE_2 23 }; 24 25 enum hws_edge_search { 26 TRAINING_EDGE_MAX, 27 TRAINING_EDGE_MIN 28 }; 29 30 enum pbs_dir { 31 PBS_TX_MODE = 0, 32 PBS_RX_MODE, 33 NUM_OF_PBS_MODES 34 }; 35 36 int ddr3_tip_pbs_rx(u32 dev_num); 37 int ddr3_tip_print_all_pbs_result(u32 dev_num); 38 int ddr3_tip_pbs_tx(u32 dev_num); 39 40 #endif /* _DDR3_TRAINING_IP_PBS_H_ */ 41
