1 #ifndef __NV30_SHADER_H__ 2 #define __NV30_SHADER_H__ 3 4 /* Vertex programs instruction set 5 * 6 * 128bit opcodes, split into 4 32-bit ones for ease of use. 7 * 8 * Non-native instructions 9 * ABS - MOV + NV40_VP_INST0_DEST_ABS 10 * POW - EX2 + MUL + LG2 11 * SUB - ADD, second source negated 12 * SWZ - MOV 13 * 14 * Register access 15 * - Only one INPUT can be accessed per-instruction (move extras into TEMPs) 16 * - Only one CONST can be accessed per-instruction (move extras into TEMPs) 17 * 18 * Relative Addressing 19 * According to the value returned for 20 * MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB 21 * 22 * there are only two address registers available. The destination in the 23 * ARL instruction is set to TEMP <n> (The temp isn't actually written). 24 * 25 * When using vanilla ARB_v_p, the proprietary driver will squish both the 26 * available ADDRESS regs into the first hardware reg in the X and Y 27 * components. 28 * 29 * To use an address reg as an index into consts, the CONST_SRC is set to 30 * (const_base + offset) and INDEX_CONST is set. 31 * 32 * To access the second address reg use ADDR_REG_SELECT_1. A particular 33 * component of the address regs is selected with ADDR_SWZ. 34 * 35 * Only one address register can be accessed per instruction. 36 * 37 * Conditional execution (see NV_vertex_program{2,3} for details) Conditional 38 * execution of an instruction is enabled by setting COND_TEST_ENABLE, and 39 * selecting the condition which will allow the test to pass with 40 * COND_{FL,LT,...}. It is possible to swizzle the values in the condition 41 * register, which allows for testing against an individual component. 42 * 43 * Branching: 44 * 45 * The BRA/CAL instructions seem to follow a slightly different opcode 46 * layout. The destination instruction ID (IADDR) overlaps a source field. 47 * Instruction ID's seem to be numbered based on the UPLOAD_FROM_ID FIFO 48 * command, and is incremented automatically on each UPLOAD_INST FIFO 49 * command. 50 * 51 * Conditional branching is achieved by using the condition tests described 52 * above. There doesn't appear to be dedicated looping instructions, but 53 * this can be done using a temp reg + conditional branching. 54 * 55 * Subroutines may be uploaded before the main program itself, but the first 56 * executed instruction is determined by the PROGRAM_START_ID FIFO command. 57 * 58 */ 59 60 /* DWORD 0 */ 61 62 /* guess that this is the same as nv40 */ 63 #define NV30_VP_INST_INDEX_INPUT (1 << 27) 64 65 #define NV30_VP_INST_ADDR_REG_SELECT_1 (1 << 24) 66 #define NV30_VP_INST_SRC2_ABS (1 << 23) /* guess */ 67 #define NV30_VP_INST_SRC1_ABS (1 << 22) /* guess */ 68 #define NV30_VP_INST_SRC0_ABS (1 << 21) /* guess */ 69 #define NV30_VP_INST_VEC_RESULT (1 << 20) 70 #define NV30_VP_INST_DEST_TEMP_ID_SHIFT 16 71 #define NV30_VP_INST_DEST_TEMP_ID_MASK (0x0F << 16) 72 #define NV30_VP_INST_COND_UPDATE_ENABLE (1<<15) 73 #define NV30_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 16) 74 #define NV30_VP_INST_COND_TEST_ENABLE (1<<14) 75 #define NV30_VP_INST_COND_SHIFT 11 76 #define NV30_VP_INST_COND_MASK (0x07 << 11) 77 #define NV30_VP_INST_COND_SWZ_X_SHIFT 9 78 #define NV30_VP_INST_COND_SWZ_X_MASK (0x03 << 9) 79 #define NV30_VP_INST_COND_SWZ_Y_SHIFT 7 80 #define NV30_VP_INST_COND_SWZ_Y_MASK (0x03 << 7) 81 #define NV30_VP_INST_COND_SWZ_Z_SHIFT 5 82 #define NV30_VP_INST_COND_SWZ_Z_MASK (0x03 << 5) 83 #define NV30_VP_INST_COND_SWZ_W_SHIFT 3 84 #define NV30_VP_INST_COND_SWZ_W_MASK (0x03 << 3) 85 #define NV30_VP_INST_COND_SWZ_ALL_SHIFT 3 86 #define NV30_VP_INST_COND_SWZ_ALL_MASK (0xFF << 3) 87 #define NV30_VP_INST_ADDR_SWZ_SHIFT 1 88 #define NV30_VP_INST_ADDR_SWZ_MASK (0x03 << 1) 89 #define NV30_VP_INST_SCA_OPCODEH_SHIFT 0 90 #define NV30_VP_INST_SCA_OPCODEH_MASK (0x01 << 0) 91 92 /* DWORD 1 */ 93 #define NV30_VP_INST_SCA_OPCODEL_SHIFT 28 94 #define NV30_VP_INST_SCA_OPCODEL_MASK (0x0F << 28) 95 #define NV30_VP_INST_VEC_OPCODE_SHIFT 23 96 #define NV30_VP_INST_VEC_OPCODE_MASK (0x1F << 23) 97 #define NV30_VP_INST_CONST_SRC_SHIFT 14 98 #define NV30_VP_INST_CONST_SRC_MASK (0xFF << 14) 99 #define NV30_VP_INST_INPUT_SRC_SHIFT 9 /*NV20*/ 100 #define NV30_VP_INST_INPUT_SRC_MASK (0x0F << 9) /*NV20*/ 101 #define NV30_VP_INST_SRC0H_SHIFT 0 /*NV20*/ 102 #define NV30_VP_INST_SRC0H_MASK (0x1FF << 0) /*NV20*/ 103 104 /* Please note: the IADDR fields overlap other fields because they are used 105 * only for branch instructions. See Branching: label above 106 * 107 * DWORD 2 108 */ 109 #define NV30_VP_INST_SRC0L_SHIFT 26 /*NV20*/ 110 #define NV30_VP_INST_SRC0L_MASK (0x3F <<26) /* NV30_VP_SRC0_LOW_MASK << 26 */ 111 #define NV30_VP_INST_SRC1_SHIFT 11 /*NV20*/ 112 #define NV30_VP_INST_SRC1_MASK (0x7FFF<<11) /*NV20*/ 113 #define NV30_VP_INST_SRC2H_SHIFT 0 /*NV20*/ 114 #define NV30_VP_INST_SRC2H_MASK (0x7FF << 0) /* NV30_VP_SRC2_HIGH_MASK >> 4*/ 115 #define NV30_VP_INST_IADDR_SHIFT 2 116 #define NV30_VP_INST_IADDR_MASK (0x1FF << 2) /* NV30_VP_SRC2_LOW_MASK << 28 */ 117 118 /* DWORD 3 */ 119 #define NV30_VP_INST_SRC2L_SHIFT 28 /*NV20*/ 120 #define NV30_VP_INST_SRC2L_MASK (0x0F <<28) /*NV20*/ 121 #define NV30_VP_INST_STEMP_WRITEMASK_SHIFT 24 122 #define NV30_VP_INST_STEMP_WRITEMASK_MASK (0x0F << 24) 123 #define NV30_VP_INST_VTEMP_WRITEMASK_SHIFT 20 124 #define NV30_VP_INST_VTEMP_WRITEMASK_MASK (0x0F << 20) 125 #define NV30_VP_INST_SDEST_WRITEMASK_SHIFT 16 126 #define NV30_VP_INST_SDEST_WRITEMASK_MASK (0x0F << 16) 127 #define NV30_VP_INST_VDEST_WRITEMASK_SHIFT 12 /*NV20*/ 128 #define NV30_VP_INST_VDEST_WRITEMASK_MASK (0x0F << 12) /*NV20*/ 129 #define NV30_VP_INST_DEST_SHIFT 2 130 #define NV30_VP_INST_DEST_MASK (0x1F << 2) 131 # define NV30_VP_INST_DEST_POS 0 132 # define NV30_VP_INST_DEST_BFC0 1 133 # define NV30_VP_INST_DEST_BFC1 2 134 # define NV30_VP_INST_DEST_COL0 3 135 # define NV30_VP_INST_DEST_COL1 4 136 # define NV30_VP_INST_DEST_FOGC 5 137 # define NV30_VP_INST_DEST_PSZ 6 138 # define NV30_VP_INST_DEST_TC(n) (8+(n)) 139 # define NV30_VP_INST_DEST_CLP(n) (17 + (n)) 140 141 /* guess that this is the same as nv40 */ 142 #define NV30_VP_INST_INDEX_CONST (1 << 1) 143 144 /* Useful to split the source selection regs into their pieces */ 145 #define NV30_VP_SRC0_HIGH_SHIFT 6 146 #define NV30_VP_SRC0_HIGH_MASK 0x00007FC0 147 #define NV30_VP_SRC0_LOW_MASK 0x0000003F 148 #define NV30_VP_SRC2_HIGH_SHIFT 4 149 #define NV30_VP_SRC2_HIGH_MASK 0x00007FF0 150 #define NV30_VP_SRC2_LOW_MASK 0x0000000F 151 152 153 /* Source-register definition - matches NV20 exactly */ 154 #define NV30_VP_SRC_NEGATE (1<<14) 155 #define NV30_VP_SRC_SWZ_X_SHIFT 12 156 #define NV30_VP_SRC_REG_SWZ_X_MASK (0x03 <<12) 157 #define NV30_VP_SRC_SWZ_Y_SHIFT 10 158 #define NV30_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10) 159 #define NV30_VP_SRC_SWZ_Z_SHIFT 8 160 #define NV30_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8) 161 #define NV30_VP_SRC_SWZ_W_SHIFT 6 162 #define NV30_VP_SRC_REG_SWZ_W_MASK (0x03 << 6) 163 #define NV30_VP_SRC_REG_SWZ_ALL_SHIFT 6 164 #define NV30_VP_SRC_REG_SWZ_ALL_MASK (0xFF << 6) 165 #define NV30_VP_SRC_TEMP_SRC_SHIFT 2 166 #define NV30_VP_SRC_REG_TEMP_ID_MASK (0x0F << 0) 167 #define NV30_VP_SRC_REG_TYPE_SHIFT 0 168 #define NV30_VP_SRC_REG_TYPE_MASK (0x03 << 0) 169 #define NV30_VP_SRC_REG_TYPE_TEMP 1 170 #define NV30_VP_SRC_REG_TYPE_INPUT 2 171 #define NV30_VP_SRC_REG_TYPE_CONST 3 /* guess */ 172 173 #include "nv30/nvfx_shader.h" 174 175 #endif 176
