1 // Copyright 2011 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_ARM_CONSTANTS_ARM_H_ 6 #define V8_ARM_CONSTANTS_ARM_H_ 7 8 #include <stdint.h> 9 10 #include "src/base/logging.h" 11 #include "src/base/macros.h" 12 #include "src/boxed-float.h" 13 #include "src/globals.h" 14 #include "src/utils.h" 15 16 // ARM EABI is required. 17 #if defined(__arm__) && !defined(__ARM_EABI__) 18 #error ARM EABI support is required. 19 #endif 20 21 namespace v8 { 22 namespace internal { 23 24 // Constant pool marker. 25 // Use UDF, the permanently undefined instruction. 26 const int kConstantPoolMarkerMask = 0xfff000f0; 27 const int kConstantPoolMarker = 0xe7f000f0; 28 const int kConstantPoolLengthMaxMask = 0xffff; 29 inline int EncodeConstantPoolLength(int length) { 30 DCHECK((length & kConstantPoolLengthMaxMask) == length); 31 return ((length & 0xfff0) << 4) | (length & 0xf); 32 } 33 inline int DecodeConstantPoolLength(int instr) { 34 DCHECK_EQ(instr & kConstantPoolMarkerMask, kConstantPoolMarker); 35 return ((instr >> 4) & 0xfff0) | (instr & 0xf); 36 } 37 38 // Number of registers in normal ARM mode. 39 const int kNumRegisters = 16; 40 41 // VFP support. 42 const int kNumVFPSingleRegisters = 32; 43 const int kNumVFPDoubleRegisters = 32; 44 const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; 45 46 // PC is register 15. 47 const int kPCRegister = 15; 48 const int kNoRegister = -1; 49 50 // Used in embedded constant pool builder - max reach in bits for 51 // various load instructions (unsigned) 52 const int kLdrMaxReachBits = 12; 53 const int kVldrMaxReachBits = 10; 54 55 // Actual value of root register is offset from the root array's start 56 // to take advantage of negative displacement values. Loads allow a uint12 57 // value with a separate sign bit (range [-4095, +4095]), so the first root 58 // is still addressable with a single load instruction. 59 constexpr int kRootRegisterBias = 4095; 60 61 // ----------------------------------------------------------------------------- 62 // Conditions. 63 64 // Defines constants and accessor classes to assemble, disassemble and 65 // simulate ARM instructions. 66 // 67 // Section references in the code refer to the "ARM Architecture Reference 68 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 69 // 70 // Constants for specific fields are defined in their respective named enums. 71 // General constants are in an anonymous enum in class Instr. 72 73 // Values for the condition field as defined in section A3.2 74 enum Condition { 75 kNoCondition = -1, 76 77 eq = 0 << 28, // Z set Equal. 78 ne = 1 << 28, // Z clear Not equal. 79 cs = 2 << 28, // C set Unsigned higher or same. 80 cc = 3 << 28, // C clear Unsigned lower. 81 mi = 4 << 28, // N set Negative. 82 pl = 5 << 28, // N clear Positive or zero. 83 vs = 6 << 28, // V set Overflow. 84 vc = 7 << 28, // V clear No overflow. 85 hi = 8 << 28, // C set, Z clear Unsigned higher. 86 ls = 9 << 28, // C clear or Z set Unsigned lower or same. 87 ge = 10 << 28, // N == V Greater or equal. 88 lt = 11 << 28, // N != V Less than. 89 gt = 12 << 28, // Z clear, N == V Greater than. 90 le = 13 << 28, // Z set or N != V Less then or equal 91 al = 14 << 28, // Always. 92 93 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). 94 kNumberOfConditions = 16, 95 96 // Aliases. 97 hs = cs, // C set Unsigned higher or same. 98 lo = cc // C clear Unsigned lower. 99 }; 100 101 102 inline Condition NegateCondition(Condition cond) { 103 DCHECK(cond != al); 104 return static_cast<Condition>(cond ^ ne); 105 } 106 107 108 // ----------------------------------------------------------------------------- 109 // Instructions encoding. 110 111 // Instr is merely used by the Assembler to distinguish 32bit integers 112 // representing instructions from usual 32 bit values. 113 // Instruction objects are pointers to 32bit values, and provide methods to 114 // access the various ISA fields. 115 typedef int32_t Instr; 116 117 118 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 119 // as defined in section A3.4 120 enum Opcode { 121 AND = 0 << 21, // Logical AND. 122 EOR = 1 << 21, // Logical Exclusive OR. 123 SUB = 2 << 21, // Subtract. 124 RSB = 3 << 21, // Reverse Subtract. 125 ADD = 4 << 21, // Add. 126 ADC = 5 << 21, // Add with Carry. 127 SBC = 6 << 21, // Subtract with Carry. 128 RSC = 7 << 21, // Reverse Subtract with Carry. 129 TST = 8 << 21, // Test. 130 TEQ = 9 << 21, // Test Equivalence. 131 CMP = 10 << 21, // Compare. 132 CMN = 11 << 21, // Compare Negated. 133 ORR = 12 << 21, // Logical (inclusive) OR. 134 MOV = 13 << 21, // Move. 135 BIC = 14 << 21, // Bit Clear. 136 MVN = 15 << 21 // Move Not. 137 }; 138 139 140 // The bits for bit 7-4 for some type 0 miscellaneous instructions. 141 enum MiscInstructionsBits74 { 142 // With bits 22-21 01. 143 BX = 1 << 4, 144 BXJ = 2 << 4, 145 BLX = 3 << 4, 146 BKPT = 7 << 4, 147 148 // With bits 22-21 11. 149 CLZ = 1 << 4 150 }; 151 152 153 // Instruction encoding bits and masks. 154 enum { 155 H = 1 << 5, // Halfword (or byte). 156 S6 = 1 << 6, // Signed (or unsigned). 157 L = 1 << 20, // Load (or store). 158 S = 1 << 20, // Set condition code (or leave unchanged). 159 W = 1 << 21, // Writeback base register (or leave unchanged). 160 A = 1 << 21, // Accumulate in multiply instruction (or not). 161 B = 1 << 22, // Unsigned byte (or word). 162 N = 1 << 22, // Long (or short). 163 U = 1 << 23, // Positive (or negative) offset/index. 164 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). 165 I = 1 << 25, // Immediate shifter operand (or not). 166 B0 = 1 << 0, 167 B4 = 1 << 4, 168 B5 = 1 << 5, 169 B6 = 1 << 6, 170 B7 = 1 << 7, 171 B8 = 1 << 8, 172 B9 = 1 << 9, 173 B10 = 1 << 10, 174 B12 = 1 << 12, 175 B16 = 1 << 16, 176 B17 = 1 << 17, 177 B18 = 1 << 18, 178 B19 = 1 << 19, 179 B20 = 1 << 20, 180 B21 = 1 << 21, 181 B22 = 1 << 22, 182 B23 = 1 << 23, 183 B24 = 1 << 24, 184 B25 = 1 << 25, 185 B26 = 1 << 26, 186 B27 = 1 << 27, 187 B28 = 1 << 28, 188 189 // Instruction bit masks. 190 kCondMask = 15 << 28, 191 kALUMask = 0x6f << 21, 192 kRdMask = 15 << 12, // In str instruction. 193 kCoprocessorMask = 15 << 8, 194 kOpCodeMask = 15 << 21, // In data-processing instructions. 195 kImm24Mask = (1 << 24) - 1, 196 kImm16Mask = (1 << 16) - 1, 197 kImm8Mask = (1 << 8) - 1, 198 kOff12Mask = (1 << 12) - 1, 199 kOff8Mask = (1 << 8) - 1 200 }; 201 202 enum BarrierOption { 203 OSHLD = 0x1, 204 OSHST = 0x2, 205 OSH = 0x3, 206 NSHLD = 0x5, 207 NSHST = 0x6, 208 NSH = 0x7, 209 ISHLD = 0x9, 210 ISHST = 0xa, 211 ISH = 0xb, 212 LD = 0xd, 213 ST = 0xe, 214 SY = 0xf, 215 }; 216 217 218 // ----------------------------------------------------------------------------- 219 // Addressing modes and instruction variants. 220 221 // Condition code updating mode. 222 enum SBit { 223 SetCC = 1 << 20, // Set condition code. 224 LeaveCC = 0 << 20 // Leave condition code unchanged. 225 }; 226 227 228 // Status register selection. 229 enum SRegister { 230 CPSR = 0 << 22, 231 SPSR = 1 << 22 232 }; 233 234 235 // Shifter types for Data-processing operands as defined in section A5.1.2. 236 enum ShiftOp { 237 LSL = 0 << 5, // Logical shift left. 238 LSR = 1 << 5, // Logical shift right. 239 ASR = 2 << 5, // Arithmetic shift right. 240 ROR = 3 << 5, // Rotate right. 241 242 // RRX is encoded as ROR with shift_imm == 0. 243 // Use a special code to make the distinction. The RRX ShiftOp is only used 244 // as an argument, and will never actually be encoded. The Assembler will 245 // detect it and emit the correct ROR shift operand with shift_imm == 0. 246 RRX = -1, 247 kNumberOfShifts = 4 248 }; 249 250 251 // Status register fields. 252 enum SRegisterField { 253 CPSR_c = CPSR | 1 << 16, 254 CPSR_x = CPSR | 1 << 17, 255 CPSR_s = CPSR | 1 << 18, 256 CPSR_f = CPSR | 1 << 19, 257 SPSR_c = SPSR | 1 << 16, 258 SPSR_x = SPSR | 1 << 17, 259 SPSR_s = SPSR | 1 << 18, 260 SPSR_f = SPSR | 1 << 19 261 }; 262 263 // Status register field mask (or'ed SRegisterField enum values). 264 typedef uint32_t SRegisterFieldMask; 265 266 267 // Memory operand addressing mode. 268 enum AddrMode { 269 // Bit encoding P U W. 270 Offset = (8|4|0) << 21, // Offset (without writeback to base). 271 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. 272 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. 273 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). 274 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. 275 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. 276 }; 277 278 279 // Load/store multiple addressing mode. 280 enum BlockAddrMode { 281 // Bit encoding P U W . 282 da = (0|0|0) << 21, // Decrement after. 283 ia = (0|4|0) << 21, // Increment after. 284 db = (8|0|0) << 21, // Decrement before. 285 ib = (8|4|0) << 21, // Increment before. 286 da_w = (0|0|1) << 21, // Decrement after with writeback to base. 287 ia_w = (0|4|1) << 21, // Increment after with writeback to base. 288 db_w = (8|0|1) << 21, // Decrement before with writeback to base. 289 ib_w = (8|4|1) << 21, // Increment before with writeback to base. 290 291 // Alias modes for comparison when writeback does not matter. 292 da_x = (0|0|0) << 21, // Decrement after. 293 ia_x = (0|4|0) << 21, // Increment after. 294 db_x = (8|0|0) << 21, // Decrement before. 295 ib_x = (8|4|0) << 21, // Increment before. 296 297 kBlockAddrModeMask = (8|4|1) << 21 298 }; 299 300 301 // Coprocessor load/store operand size. 302 enum LFlag { 303 Long = 1 << 22, // Long load/store coprocessor. 304 Short = 0 << 22 // Short load/store coprocessor. 305 }; 306 307 // Neon sizes. 308 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 }; 309 310 // NEON data type 311 enum NeonDataType { 312 NeonS8 = 0, 313 NeonS16 = 1, 314 NeonS32 = 2, 315 // Gap to make it easier to extract U and size. 316 NeonU8 = 4, 317 NeonU16 = 5, 318 NeonU32 = 6 319 }; 320 321 inline int NeonU(NeonDataType dt) { return static_cast<int>(dt) >> 2; } 322 inline int NeonSz(NeonDataType dt) { return static_cast<int>(dt) & 0x3; } 323 324 // Convert sizes to data types (U bit is clear). 325 inline NeonDataType NeonSizeToDataType(NeonSize size) { 326 DCHECK_NE(Neon64, size); 327 return static_cast<NeonDataType>(size); 328 } 329 330 inline NeonSize NeonDataTypeToSize(NeonDataType dt) { 331 return static_cast<NeonSize>(NeonSz(dt)); 332 } 333 334 enum NeonListType { 335 nlt_1 = 0x7, 336 nlt_2 = 0xA, 337 nlt_3 = 0x6, 338 nlt_4 = 0x2 339 }; 340 341 // ----------------------------------------------------------------------------- 342 // Supervisor Call (svc) specific support. 343 344 // Special Software Interrupt codes when used in the presence of the ARM 345 // simulator. 346 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 347 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 348 enum SoftwareInterruptCodes { 349 // transition to C code 350 kCallRtRedirected = 0x10, 351 // break point 352 kBreakpoint = 0x20, 353 // stop 354 kStopCode = 1 << 23 355 }; 356 const uint32_t kStopCodeMask = kStopCode - 1; 357 const uint32_t kMaxStopCode = kStopCode - 1; 358 const int32_t kDefaultStopCode = -1; 359 360 361 // Type of VFP register. Determines register encoding. 362 enum VFPRegPrecision { 363 kSinglePrecision = 0, 364 kDoublePrecision = 1, 365 kSimd128Precision = 2 366 }; 367 368 // VFP FPSCR constants. 369 enum VFPConversionMode { 370 kFPSCRRounding = 0, 371 kDefaultRoundToZero = 1 372 }; 373 374 // This mask does not include the "inexact" or "input denormal" cumulative 375 // exceptions flags, because we usually don't want to check for it. 376 const uint32_t kVFPExceptionMask = 0xf; 377 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; 378 const uint32_t kVFPOverflowExceptionBit = 1 << 2; 379 const uint32_t kVFPUnderflowExceptionBit = 1 << 3; 380 const uint32_t kVFPInexactExceptionBit = 1 << 4; 381 const uint32_t kVFPFlushToZeroMask = 1 << 24; 382 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25; 383 384 const uint32_t kVFPNConditionFlagBit = 1 << 31; 385 const uint32_t kVFPZConditionFlagBit = 1 << 30; 386 const uint32_t kVFPCConditionFlagBit = 1 << 29; 387 const uint32_t kVFPVConditionFlagBit = 1 << 28; 388 389 390 // VFP rounding modes. See ARM DDI 0406B Page A2-29. 391 enum VFPRoundingMode { 392 RN = 0 << 22, // Round to Nearest. 393 RP = 1 << 22, // Round towards Plus Infinity. 394 RM = 2 << 22, // Round towards Minus Infinity. 395 RZ = 3 << 22, // Round towards zero. 396 397 // Aliases. 398 kRoundToNearest = RN, 399 kRoundToPlusInf = RP, 400 kRoundToMinusInf = RM, 401 kRoundToZero = RZ 402 }; 403 404 const uint32_t kVFPRoundingModeMask = 3 << 22; 405 406 enum CheckForInexactConversion { 407 kCheckForInexactConversion, 408 kDontCheckForInexactConversion 409 }; 410 411 // ----------------------------------------------------------------------------- 412 // Hints. 413 414 // Branch hints are not used on the ARM. They are defined so that they can 415 // appear in shared function signatures, but will be ignored in ARM 416 // implementations. 417 enum Hint { no_hint }; 418 419 // Hints are not used on the arm. Negating is trivial. 420 inline Hint NegateHint(Hint ignored) { return no_hint; } 421 422 423 // ----------------------------------------------------------------------------- 424 // Instruction abstraction. 425 426 // The class Instruction enables access to individual fields defined in the ARM 427 // architecture instruction set encoding as described in figure A3-1. 428 // Note that the Assembler uses typedef int32_t Instr. 429 // 430 // Example: Test whether the instruction at ptr does set the condition code 431 // bits. 432 // 433 // bool InstructionSetsConditionCodes(byte* ptr) { 434 // Instruction* instr = Instruction::At(ptr); 435 // int type = instr->TypeValue(); 436 // return ((type == 0) || (type == 1)) && instr->HasS(); 437 // } 438 // 439 440 constexpr uint8_t kInstrSize = 4; 441 constexpr uint8_t kInstrSizeLog2 = 2; 442 443 class Instruction { 444 public: 445 // Difference between address of current opcode and value read from pc 446 // register. 447 static constexpr int kPcLoadDelta = 8; 448 449 // Helper macro to define static accessors. 450 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 451 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 452 static inline return_type Name(Instr instr) { \ 453 char* temp = reinterpret_cast<char*>(&instr); \ 454 return reinterpret_cast<Instruction*>(temp)->Name(); \ 455 } 456 457 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 458 459 // Get the raw instruction bits. 460 inline Instr InstructionBits() const { 461 return *reinterpret_cast<const Instr*>(this); 462 } 463 464 // Set the raw instruction bits to value. 465 inline void SetInstructionBits(Instr value) { 466 *reinterpret_cast<Instr*>(this) = value; 467 } 468 469 // Extract a single bit from the instruction bits and return it as bit 0 in 470 // the result. 471 inline int Bit(int nr) const { 472 return (InstructionBits() >> nr) & 1; 473 } 474 475 // Extract a bit field <hi:lo> from the instruction bits and return it in the 476 // least-significant bits of the result. 477 inline int Bits(int hi, int lo) const { 478 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 479 } 480 481 // Read a bit field <hi:lo>, leaving its position unchanged in the result. 482 inline int BitField(int hi, int lo) const { 483 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 484 } 485 486 // Static support. 487 488 // Extract a single bit from the instruction bits and return it as bit 0 in 489 // the result. 490 static inline int Bit(Instr instr, int nr) { 491 return (instr >> nr) & 1; 492 } 493 494 // Extract a bit field <hi:lo> from the instruction bits and return it in the 495 // least-significant bits of the result. 496 static inline int Bits(Instr instr, int hi, int lo) { 497 return (instr >> lo) & ((2 << (hi - lo)) - 1); 498 } 499 500 // Read a bit field <hi:lo>, leaving its position unchanged in the result. 501 static inline int BitField(Instr instr, int hi, int lo) { 502 return instr & (((2 << (hi - lo)) - 1) << lo); 503 } 504 505 // Accessors for the different named fields used in the ARM encoding. 506 // The naming of these accessor corresponds to figure A3-1. 507 // 508 // Two kind of accessors are declared: 509 // - <Name>Field() will return the raw field, i.e. the field's bits at their 510 // original place in the instruction encoding. 511 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 512 // 0xC0810002 ConditionField(instr) will return 0xC0000000. 513 // - <Name>Value() will return the field value, shifted back to bit 0. 514 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 515 // 0xC0810002 ConditionField(instr) will return 0xC. 516 517 518 // Generally applicable fields 519 inline int ConditionValue() const { return Bits(31, 28); } 520 inline Condition ConditionField() const { 521 return static_cast<Condition>(BitField(31, 28)); 522 } 523 DECLARE_STATIC_TYPED_ACCESSOR(int, ConditionValue); 524 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); 525 526 inline int TypeValue() const { return Bits(27, 25); } 527 inline int SpecialValue() const { return Bits(27, 23); } 528 529 inline int RnValue() const { return Bits(19, 16); } 530 DECLARE_STATIC_ACCESSOR(RnValue); 531 inline int RdValue() const { return Bits(15, 12); } 532 DECLARE_STATIC_ACCESSOR(RdValue); 533 534 inline int CoprocessorValue() const { return Bits(11, 8); } 535 // Support for VFP. 536 // Vn(19-16) | Vd(15-12) | Vm(3-0) 537 inline int VnValue() const { return Bits(19, 16); } 538 inline int VmValue() const { return Bits(3, 0); } 539 inline int VdValue() const { return Bits(15, 12); } 540 inline int NValue() const { return Bit(7); } 541 inline int MValue() const { return Bit(5); } 542 inline int DValue() const { return Bit(22); } 543 inline int RtValue() const { return Bits(15, 12); } 544 inline int PValue() const { return Bit(24); } 545 inline int UValue() const { return Bit(23); } 546 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } 547 inline int Opc2Value() const { return Bits(19, 16); } 548 inline int Opc3Value() const { return Bits(7, 6); } 549 inline int SzValue() const { return Bit(8); } 550 inline int VLValue() const { return Bit(20); } 551 inline int VCValue() const { return Bit(8); } 552 inline int VAValue() const { return Bits(23, 21); } 553 inline int VBValue() const { return Bits(6, 5); } 554 inline int VFPNRegValue(VFPRegPrecision pre) { 555 return VFPGlueRegValue(pre, 16, 7); 556 } 557 inline int VFPMRegValue(VFPRegPrecision pre) { 558 return VFPGlueRegValue(pre, 0, 5); 559 } 560 inline int VFPDRegValue(VFPRegPrecision pre) { 561 return VFPGlueRegValue(pre, 12, 22); 562 } 563 564 // Fields used in Data processing instructions 565 inline int OpcodeValue() const { 566 return static_cast<Opcode>(Bits(24, 21)); 567 } 568 inline Opcode OpcodeField() const { 569 return static_cast<Opcode>(BitField(24, 21)); 570 } 571 inline int SValue() const { return Bit(20); } 572 // with register 573 inline int RmValue() const { return Bits(3, 0); } 574 DECLARE_STATIC_ACCESSOR(RmValue); 575 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 576 inline ShiftOp ShiftField() const { 577 return static_cast<ShiftOp>(BitField(6, 5)); 578 } 579 inline int RegShiftValue() const { return Bit(4); } 580 inline int RsValue() const { return Bits(11, 8); } 581 inline int ShiftAmountValue() const { return Bits(11, 7); } 582 // with immediate 583 inline int RotateValue() const { return Bits(11, 8); } 584 DECLARE_STATIC_ACCESSOR(RotateValue); 585 inline int Immed8Value() const { return Bits(7, 0); } 586 DECLARE_STATIC_ACCESSOR(Immed8Value); 587 inline int Immed4Value() const { return Bits(19, 16); } 588 inline int ImmedMovwMovtValue() const { 589 return Immed4Value() << 12 | Offset12Value(); } 590 DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue); 591 592 // Fields used in Load/Store instructions 593 inline int PUValue() const { return Bits(24, 23); } 594 inline int PUField() const { return BitField(24, 23); } 595 inline int BValue() const { return Bit(22); } 596 inline int WValue() const { return Bit(21); } 597 inline int LValue() const { return Bit(20); } 598 // with register uses same fields as Data processing instructions above 599 // with immediate 600 inline int Offset12Value() const { return Bits(11, 0); } 601 // multiple 602 inline int RlistValue() const { return Bits(15, 0); } 603 // extra loads and stores 604 inline int SignValue() const { return Bit(6); } 605 inline int HValue() const { return Bit(5); } 606 inline int ImmedHValue() const { return Bits(11, 8); } 607 inline int ImmedLValue() const { return Bits(3, 0); } 608 609 // Fields used in Branch instructions 610 inline int LinkValue() const { return Bit(24); } 611 inline int SImmed24Value() const { 612 return signed_bitextract_32(23, 0, InstructionBits()); 613 } 614 615 bool IsBranch() { return Bit(27) == 1 && Bit(25) == 1; } 616 617 int GetBranchOffset() { 618 DCHECK(IsBranch()); 619 return SImmed24Value() * kInstrSize; 620 } 621 622 void SetBranchOffset(int32_t branch_offset) { 623 DCHECK(IsBranch()); 624 DCHECK_EQ(branch_offset % kInstrSize, 0); 625 int32_t new_imm24 = branch_offset / kInstrSize; 626 CHECK(is_int24(new_imm24)); 627 SetInstructionBits((InstructionBits() & ~(kImm24Mask)) | 628 (new_imm24 & kImm24Mask)); 629 } 630 631 // Fields used in Software interrupt instructions 632 inline SoftwareInterruptCodes SvcValue() const { 633 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 634 } 635 636 // Test for special encodings of type 0 instructions (extra loads and stores, 637 // as well as multiplications). 638 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 639 640 // Test for miscellaneous instructions encodings of type 0 instructions. 641 inline bool IsMiscType0() const { return (Bit(24) == 1) 642 && (Bit(23) == 0) 643 && (Bit(20) == 0) 644 && ((Bit(7) == 0)); } 645 646 // Test for nop-like instructions which fall under type 1. 647 inline bool IsNopLikeType1() const { return Bits(24, 8) == 0x120F0; } 648 649 // Test for a stop instruction. 650 inline bool IsStop() const { 651 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); 652 } 653 654 // Special accessors that test for existence of a value. 655 inline bool HasS() const { return SValue() == 1; } 656 inline bool HasB() const { return BValue() == 1; } 657 inline bool HasW() const { return WValue() == 1; } 658 inline bool HasL() const { return LValue() == 1; } 659 inline bool HasU() const { return UValue() == 1; } 660 inline bool HasSign() const { return SignValue() == 1; } 661 inline bool HasH() const { return HValue() == 1; } 662 inline bool HasLink() const { return LinkValue() == 1; } 663 664 // Decode the double immediate from a vmov instruction. 665 Float64 DoubleImmedVmov() const; 666 667 // Instructions are read of out a code stream. The only way to get a 668 // reference to an instruction is to convert a pointer. There is no way 669 // to allocate or create instances of class Instruction. 670 // Use the At(pc) function to create references to Instruction. 671 static Instruction* At(Address pc) { 672 return reinterpret_cast<Instruction*>(pc); 673 } 674 675 676 private: 677 // Join split register codes, depending on register precision. 678 // four_bit is the position of the least-significant bit of the four 679 // bit specifier. one_bit is the position of the additional single bit 680 // specifier. 681 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { 682 if (pre == kSinglePrecision) { 683 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); 684 } else { 685 int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); 686 if (pre == kDoublePrecision) { 687 return reg_num; 688 } 689 DCHECK_EQ(kSimd128Precision, pre); 690 DCHECK_EQ(reg_num & 1, 0); 691 return reg_num / 2; 692 } 693 } 694 695 // We need to prevent the creation of instances of class Instruction. 696 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 697 }; 698 699 700 // Helper functions for converting between register numbers and names. 701 class Registers { 702 public: 703 // Return the name of the register. 704 static const char* Name(int reg); 705 706 // Lookup the register number for the name provided. 707 static int Number(const char* name); 708 709 struct RegisterAlias { 710 int reg; 711 const char* name; 712 }; 713 714 private: 715 static const char* names_[kNumRegisters]; 716 static const RegisterAlias aliases_[]; 717 }; 718 719 // Helper functions for converting between VFP register numbers and names. 720 class VFPRegisters { 721 public: 722 // Return the name of the register. 723 static const char* Name(int reg, bool is_double); 724 725 // Lookup the register number for the name provided. 726 // Set flag pointed by is_double to true if register 727 // is double-precision. 728 static int Number(const char* name, bool* is_double); 729 730 private: 731 static const char* names_[kNumVFPRegisters]; 732 }; 733 734 // Relative jumps on ARM can address 32 MB. 735 constexpr size_t kMaxPCRelativeCodeRangeInMB = 32; 736 737 } // namespace internal 738 } // namespace v8 739 740 #endif // V8_ARM_CONSTANTS_ARM_H_ 741
