| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 137 unsigned NewImm;
140 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
141 Offset = SignExtend64<16>(NewImm);
|
| MipsSERegisterInfo.cpp | 198 unsigned NewImm = 0;
203 OffsetBitSize == 16 ? &NewImm : nullptr);
208 Offset = SignExtend64<16>(NewImm);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 137 unsigned NewImm;
140 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
141 Offset = SignExtend64<16>(NewImm);
|
| MipsSERegisterInfo.cpp | 244 unsigned NewImm = 0;
249 OffsetBitSize == 16 ? &NewImm : nullptr);
254 Offset = SignExtend64<16>(NewImm);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 107 // (NewReg, NewImm) = ($at, lo(Ox10000))
110 unsigned& NewReg, int& NewImm,
116 NewImm = OrigImm;
133 NewImm = ImmLo;
150 int NewImm = 0;
181 ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB,
184 .addReg(NewReg).addImm(NewImm);
280 int NewImm = 0;
298 ATUsed = expandRegLargeImmPair(Mips::SP, StackSize, NewReg, NewImm, MBB,
301 .addReg(NewReg).addImm(NewImm);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionOptimizer.cpp | 246 const int NewImm = std::abs(OldImm + Correction);
255 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
398 // 1) (a >= {NewImm} && ...) || (a <= {NewImm} && ...)
399 // 2) (a <= {NewImm} && ...) || (a >= {NewImm} && ...)
419 // 1) (a <= {NewImm} && ...) || (a > {NewImm} && ...)
420 // 2) (a < {NewImm} && ...) || (a >= {NewImm} && ...
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ConditionOptimizer.cpp | 257 const int NewImm = std::abs(OldImm + Correction);
266 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
409 // 1) (a >= {NewImm} && ...) || (a <= {NewImm} && ...)
410 // 2) (a <= {NewImm} && ...) || (a >= {NewImm} && ...)
430 // 1) (a <= {NewImm} && ...) || (a > {NewImm} && ...)
431 // 2) (a < {NewImm} && ...) || (a >= {NewImm} && ...
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.cpp | 167 unsigned NewImm = Imm;
172 ShuffleMask.push_back(l + 4 + (NewImm & 3));
173 NewImm >>= 2;
181 unsigned NewImm = Imm;
183 ShuffleMask.push_back(l + (NewImm & 3));
184 NewImm >>= 2;
208 unsigned NewImm = Imm;
213 ShuffleMask.push_back(NewImm % NumLaneElts + s + l);
214 NewImm /= NumLaneElts;
217 if (NumLaneElts == 4) NewImm = Imm; // reload im
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.cpp | 164 unsigned NewImm = Imm;
167 ShuffleMask.push_back(NewImm % NumLaneElts + l);
168 NewImm /= NumLaneElts;
170 if (NumLaneElts == 4) NewImm = Imm; // reload imm
179 unsigned NewImm = Imm;
184 ShuffleMask.push_back(l + 4 + (NewImm & 3));
185 NewImm >>= 2;
195 unsigned NewImm = Imm;
197 ShuffleMask.push_back(l + (NewImm & 3));
198 NewImm >>= 2
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 557 int32_t NewImm;
558 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
566 MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
