1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * Texas Instruments, <www.ti.com> 5 * 6 * Authors: 7 * Aneesh V <aneesh (at) ti.com> 8 * 9 * Derived from OMAP3 work by 10 * Richard Woodruff <r-woodruff2 (at) ti.com> 11 * Syed Mohammed Khasim <x0khasim (at) ti.com> 12 */ 13 14 #ifndef _OMAP4_H_ 15 #define _OMAP4_H_ 16 17 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 18 #include <asm/types.h> 19 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 20 21 #include <linux/sizes.h> 22 23 /* 24 * L4 Peripherals - L4 Wakeup and L4 Core now 25 */ 26 #define OMAP44XX_L4_CORE_BASE 0x4A000000 27 #define OMAP44XX_L4_WKUP_BASE 0x4A300000 28 #define OMAP44XX_L4_PER_BASE 0x48000000 29 30 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 31 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 32 #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START 33 #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END 34 35 /* CONTROL_ID_CODE */ 36 #define CONTROL_ID_CODE 0x4A002204 37 38 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F 39 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F 40 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F 41 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F 42 #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F 43 #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F 44 #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F 45 #define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F 46 47 /* UART */ 48 #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) 49 #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) 50 #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) 51 52 /* General Purpose Timers */ 53 #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) 54 #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) 55 #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) 56 57 /* Watchdog Timer2 - MPU watchdog */ 58 #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) 59 60 /* 61 * Hardware Register Details 62 */ 63 64 /* Watchdog Timer */ 65 #define WD_UNLOCK1 0xAAAA 66 #define WD_UNLOCK2 0x5555 67 68 /* GP Timer */ 69 #define TCLR_ST (0x1 << 0) 70 #define TCLR_AR (0x1 << 1) 71 #define TCLR_PRE (0x1 << 5) 72 73 /* Control Module */ 74 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 75 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 76 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 77 #define CONTROL_EFUSE_2_OVERRIDE 0x99084000 78 79 /* LPDDR2 IO regs */ 80 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 81 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 82 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 83 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 84 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F 85 86 /* CONTROL_EFUSE_2 */ 87 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 88 89 #define MMC1_PWRDNZ (1 << 26) 90 #define MMC1_PBIASLITE_PWRDNZ (1 << 22) 91 #define MMC1_PBIASLITE_VMODE (1 << 21) 92 93 #ifndef __ASSEMBLY__ 94 95 struct s32ktimer { 96 unsigned char res[0x10]; 97 unsigned int s32k_cr; /* 0x10 */ 98 }; 99 100 #define DEVICE_TYPE_SHIFT (0x8) 101 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 102 103 #endif /* __ASSEMBLY__ */ 104 105 /* 106 * Non-secure SRAM Addresses 107 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 108 * at 0x40304000(EMU base) so that our code works for both EMU and GP 109 */ 110 #define NON_SECURE_SRAM_START 0x40304000 111 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 112 #define NON_SECURE_SRAM_IMG_END 0x4030C000 113 #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) 114 /* base address for indirect vectors (internal boot mode) */ 115 #define SRAM_ROM_VECT_BASE 0x4030D000 116 117 /* ABB settings */ 118 #define OMAP_ABB_SETTLING_TIME 50 119 #define OMAP_ABB_CLOCK_CYCLES 16 120 121 /* ABB tranxdone mask */ 122 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 123 124 #define OMAP44XX_SAR_RAM_BASE 0x4a326000 125 #define OMAP_REBOOT_REASON_OFFSET 0xA0C 126 #define OMAP_REBOOT_REASON_SIZE 0x0F 127 128 /* Boot parameters */ 129 #ifndef __ASSEMBLY__ 130 struct omap_boot_parameters { 131 unsigned int boot_message; 132 unsigned int boot_device_descriptor; 133 unsigned char boot_device; 134 unsigned char reset_reason; 135 unsigned char ch_flags; 136 }; 137 138 int omap_reboot_mode(char *mode, unsigned int length); 139 int omap_reboot_mode_clear(void); 140 int omap_reboot_mode_store(char *mode); 141 #endif 142 143 #endif 144
