1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Contains the definition of a TargetInstrInfo class that is common 12 /// to all AMD GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H 17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H 18 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #define GET_INSTRINFO_ENUM 23 #define GET_INSTRINFO_OPERAND_ENUM 24 #include "AMDGPUGenInstrInfo.inc" 25 26 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT 27 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT 28 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE 29 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE 30 31 namespace llvm { 32 33 class AMDGPUSubtarget; 34 class MachineFunction; 35 class MachineInstr; 36 class MachineInstrBuilder; 37 38 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { 39 private: 40 const AMDGPUSubtarget &ST; 41 42 virtual void anchor(); 43 44 public: 45 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st); 46 47 bool enableClusterLoads() const override; 48 49 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 50 int64_t Offset1, int64_t Offset2, 51 unsigned NumLoads) const override; 52 53 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction. 54 /// Return -1 if the target-specific opcode for the pseudo instruction does 55 /// not exist. If Opcode is not a pseudo instruction, this is identity. 56 int pseudoToMCOpcode(int Opcode) const; 57 58 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the 59 /// equivalent opcode that writes \p Channels Channels. 60 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const; 61 }; 62 63 namespace AMDGPU { 64 LLVM_READONLY 65 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 66 } // End namespace AMDGPU 67 68 } // End llvm namespace 69 70 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63) 71 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62) 72 73 #endif 74
