1 /** @file 2 PCI command register operations supporting functions declaration for PCI Bus module. 3 4 Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 16 #ifndef _EFI_PCI_COMMAND_H_ 17 #define _EFI_PCI_COMMAND_H_ 18 19 // 20 // The PCI Command register bits owned by PCI Bus driver. 21 // 22 // They should be cleared at the beginning. The other registers 23 // are owned by chipset, we should not touch them. 24 // 25 #define EFI_PCI_COMMAND_BITS_OWNED ( \ 26 EFI_PCI_COMMAND_IO_SPACE | \ 27 EFI_PCI_COMMAND_MEMORY_SPACE | \ 28 EFI_PCI_COMMAND_BUS_MASTER | \ 29 EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \ 30 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \ 31 EFI_PCI_COMMAND_FAST_BACK_TO_BACK \ 32 ) 33 34 // 35 // The PCI Bridge Control register bits owned by PCI Bus driver. 36 // 37 // They should be cleared at the beginning. The other registers 38 // are owned by chipset, we should not touch them. 39 // 40 #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \ 41 EFI_PCI_BRIDGE_CONTROL_ISA | \ 42 EFI_PCI_BRIDGE_CONTROL_VGA | \ 43 EFI_PCI_BRIDGE_CONTROL_VGA_16 | \ 44 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \ 45 ) 46 47 // 48 // The PCCard Bridge Control register bits owned by PCI Bus driver. 49 // 50 // They should be cleared at the beginning. The other registers 51 // are owned by chipset, we should not touch them. 52 // 53 #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \ 54 EFI_PCI_BRIDGE_CONTROL_ISA | \ 55 EFI_PCI_BRIDGE_CONTROL_VGA | \ 56 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \ 57 ) 58 59 60 #define EFI_GET_REGISTER 1 61 #define EFI_SET_REGISTER 2 62 #define EFI_ENABLE_REGISTER 3 63 #define EFI_DISABLE_REGISTER 4 64 65 /** 66 Operate the PCI register via PciIo function interface. 67 68 @param PciIoDevice Pointer to instance of PCI_IO_DEVICE. 69 @param Command Operator command. 70 @param Offset The address within the PCI configuration space for the PCI controller. 71 @param Operation Type of Operation. 72 @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER. 73 74 @return Status of PciIo operation. 75 76 **/ 77 EFI_STATUS 78 PciOperateRegister ( 79 IN PCI_IO_DEVICE *PciIoDevice, 80 IN UINT16 Command, 81 IN UINT8 Offset, 82 IN UINT8 Operation, 83 OUT UINT16 *PtrCommand 84 ); 85 86 /** 87 Check the cpability supporting by given device. 88 89 @param PciIoDevice Pointer to instance of PCI_IO_DEVICE. 90 91 @retval TRUE Cpability supportted. 92 @retval FALSE Cpability not supportted. 93 94 **/ 95 BOOLEAN 96 PciCapabilitySupport ( 97 IN PCI_IO_DEVICE *PciIoDevice 98 ); 99 100 /** 101 Locate capability register block per capability ID. 102 103 @param PciIoDevice A pointer to the PCI_IO_DEVICE. 104 @param CapId The capability ID. 105 @param Offset A pointer to the offset returned. 106 @param NextRegBlock A pointer to the next block returned. 107 108 @retval EFI_SUCCESS Successfuly located capability register block. 109 @retval EFI_UNSUPPORTED Pci device does not support capability. 110 @retval EFI_NOT_FOUND Pci device support but can not find register block. 111 112 **/ 113 EFI_STATUS 114 LocateCapabilityRegBlock ( 115 IN PCI_IO_DEVICE *PciIoDevice, 116 IN UINT8 CapId, 117 IN OUT UINT8 *Offset, 118 OUT UINT8 *NextRegBlock OPTIONAL 119 ); 120 121 /** 122 Locate PciExpress capability register block per capability ID. 123 124 @param PciIoDevice A pointer to the PCI_IO_DEVICE. 125 @param CapId The capability ID. 126 @param Offset A pointer to the offset returned. 127 @param NextRegBlock A pointer to the next block returned. 128 129 @retval EFI_SUCCESS Successfuly located capability register block. 130 @retval EFI_UNSUPPORTED Pci device does not support capability. 131 @retval EFI_NOT_FOUND Pci device support but can not find register block. 132 133 **/ 134 EFI_STATUS 135 LocatePciExpressCapabilityRegBlock ( 136 IN PCI_IO_DEVICE *PciIoDevice, 137 IN UINT16 CapId, 138 IN OUT UINT32 *Offset, 139 OUT UINT32 *NextRegBlock OPTIONAL 140 ); 141 142 /** 143 Macro that reads command register. 144 145 @param a[in] Pointer to instance of PCI_IO_DEVICE. 146 @param b[out] Pointer to the 16-bit value read from command register. 147 148 @return status of PciIo operation 149 150 **/ 151 #define PCI_READ_COMMAND_REGISTER(a,b) \ 152 PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b) 153 154 /** 155 Macro that writes command register. 156 157 @param a[in] Pointer to instance of PCI_IO_DEVICE. 158 @param b[in] The 16-bit value written into command register. 159 160 @return status of PciIo operation 161 162 **/ 163 #define PCI_SET_COMMAND_REGISTER(a,b) \ 164 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL) 165 166 /** 167 Macro that enables command register. 168 169 @param a[in] Pointer to instance of PCI_IO_DEVICE. 170 @param b[in] The enabled value written into command register. 171 172 @return status of PciIo operation 173 174 **/ 175 #define PCI_ENABLE_COMMAND_REGISTER(a,b) \ 176 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL) 177 178 /** 179 Macro that disalbes command register. 180 181 @param a[in] Pointer to instance of PCI_IO_DEVICE. 182 @param b[in] The disabled value written into command register. 183 184 @return status of PciIo operation 185 186 **/ 187 #define PCI_DISABLE_COMMAND_REGISTER(a,b) \ 188 PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL) 189 190 /** 191 Macro that reads PCI bridge control register. 192 193 @param a[in] Pointer to instance of PCI_IO_DEVICE. 194 @param b[out] The 16-bit value read from control register. 195 196 @return status of PciIo operation 197 198 **/ 199 #define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \ 200 PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b) 201 202 /** 203 Macro that writes PCI bridge control register. 204 205 @param a[in] Pointer to instance of PCI_IO_DEVICE. 206 @param b[in] The 16-bit value written into control register. 207 208 @return status of PciIo operation 209 210 **/ 211 #define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \ 212 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL) 213 214 /** 215 Macro that enables PCI bridge control register. 216 217 @param a[in] Pointer to instance of PCI_IO_DEVICE. 218 @param b[in] The enabled value written into command register. 219 220 @return status of PciIo operation 221 222 **/ 223 #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \ 224 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL) 225 226 /** 227 Macro that disalbes PCI bridge control register. 228 229 @param a[in] Pointer to instance of PCI_IO_DEVICE. 230 @param b[in] The disabled value written into command register. 231 232 @return status of PciIo operation 233 234 **/ 235 #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \ 236 PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL) 237 238 #endif 239
