1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef _TEGRA124_PINMUX_H_ 7 #define _TEGRA124_PINMUX_H_ 8 9 enum pmux_pingrp { 10 PMUX_PINGRP_ULPI_DATA0_PO1, 11 PMUX_PINGRP_ULPI_DATA1_PO2, 12 PMUX_PINGRP_ULPI_DATA2_PO3, 13 PMUX_PINGRP_ULPI_DATA3_PO4, 14 PMUX_PINGRP_ULPI_DATA4_PO5, 15 PMUX_PINGRP_ULPI_DATA5_PO6, 16 PMUX_PINGRP_ULPI_DATA6_PO7, 17 PMUX_PINGRP_ULPI_DATA7_PO0, 18 PMUX_PINGRP_ULPI_CLK_PY0, 19 PMUX_PINGRP_ULPI_DIR_PY1, 20 PMUX_PINGRP_ULPI_NXT_PY2, 21 PMUX_PINGRP_ULPI_STP_PY3, 22 PMUX_PINGRP_DAP3_FS_PP0, 23 PMUX_PINGRP_DAP3_DIN_PP1, 24 PMUX_PINGRP_DAP3_DOUT_PP2, 25 PMUX_PINGRP_DAP3_SCLK_PP3, 26 PMUX_PINGRP_PV0, 27 PMUX_PINGRP_PV1, 28 PMUX_PINGRP_SDMMC1_CLK_PZ0, 29 PMUX_PINGRP_SDMMC1_CMD_PZ1, 30 PMUX_PINGRP_SDMMC1_DAT3_PY4, 31 PMUX_PINGRP_SDMMC1_DAT2_PY5, 32 PMUX_PINGRP_SDMMC1_DAT1_PY6, 33 PMUX_PINGRP_SDMMC1_DAT0_PY7, 34 PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), 35 PMUX_PINGRP_CLK2_REQ_PCC5, 36 PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), 37 PMUX_PINGRP_DDC_SCL_PV4, 38 PMUX_PINGRP_DDC_SDA_PV5, 39 PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), 40 PMUX_PINGRP_UART2_TXD_PC2, 41 PMUX_PINGRP_UART2_RTS_N_PJ6, 42 PMUX_PINGRP_UART2_CTS_N_PJ5, 43 PMUX_PINGRP_UART3_TXD_PW6, 44 PMUX_PINGRP_UART3_RXD_PW7, 45 PMUX_PINGRP_UART3_CTS_N_PA1, 46 PMUX_PINGRP_UART3_RTS_N_PC0, 47 PMUX_PINGRP_PU0, 48 PMUX_PINGRP_PU1, 49 PMUX_PINGRP_PU2, 50 PMUX_PINGRP_PU3, 51 PMUX_PINGRP_PU4, 52 PMUX_PINGRP_PU5, 53 PMUX_PINGRP_PU6, 54 PMUX_PINGRP_GEN1_I2C_SDA_PC5, 55 PMUX_PINGRP_GEN1_I2C_SCL_PC4, 56 PMUX_PINGRP_DAP4_FS_PP4, 57 PMUX_PINGRP_DAP4_DIN_PP5, 58 PMUX_PINGRP_DAP4_DOUT_PP6, 59 PMUX_PINGRP_DAP4_SCLK_PP7, 60 PMUX_PINGRP_CLK3_OUT_PEE0, 61 PMUX_PINGRP_CLK3_REQ_PEE1, 62 PMUX_PINGRP_PC7, 63 PMUX_PINGRP_PI5, 64 PMUX_PINGRP_PI7, 65 PMUX_PINGRP_PK0, 66 PMUX_PINGRP_PK1, 67 PMUX_PINGRP_PJ0, 68 PMUX_PINGRP_PJ2, 69 PMUX_PINGRP_PK3, 70 PMUX_PINGRP_PK4, 71 PMUX_PINGRP_PK2, 72 PMUX_PINGRP_PI3, 73 PMUX_PINGRP_PI6, 74 PMUX_PINGRP_PG0, 75 PMUX_PINGRP_PG1, 76 PMUX_PINGRP_PG2, 77 PMUX_PINGRP_PG3, 78 PMUX_PINGRP_PG4, 79 PMUX_PINGRP_PG5, 80 PMUX_PINGRP_PG6, 81 PMUX_PINGRP_PG7, 82 PMUX_PINGRP_PH0, 83 PMUX_PINGRP_PH1, 84 PMUX_PINGRP_PH2, 85 PMUX_PINGRP_PH3, 86 PMUX_PINGRP_PH4, 87 PMUX_PINGRP_PH5, 88 PMUX_PINGRP_PH6, 89 PMUX_PINGRP_PH7, 90 PMUX_PINGRP_PJ7, 91 PMUX_PINGRP_PB0, 92 PMUX_PINGRP_PB1, 93 PMUX_PINGRP_PK7, 94 PMUX_PINGRP_PI0, 95 PMUX_PINGRP_PI1, 96 PMUX_PINGRP_PI2, 97 PMUX_PINGRP_PI4, 98 PMUX_PINGRP_GEN2_I2C_SCL_PT5, 99 PMUX_PINGRP_GEN2_I2C_SDA_PT6, 100 PMUX_PINGRP_SDMMC4_CLK_PCC4, 101 PMUX_PINGRP_SDMMC4_CMD_PT7, 102 PMUX_PINGRP_SDMMC4_DAT0_PAA0, 103 PMUX_PINGRP_SDMMC4_DAT1_PAA1, 104 PMUX_PINGRP_SDMMC4_DAT2_PAA2, 105 PMUX_PINGRP_SDMMC4_DAT3_PAA3, 106 PMUX_PINGRP_SDMMC4_DAT4_PAA4, 107 PMUX_PINGRP_SDMMC4_DAT5_PAA5, 108 PMUX_PINGRP_SDMMC4_DAT6_PAA6, 109 PMUX_PINGRP_SDMMC4_DAT7_PAA7, 110 PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), 111 PMUX_PINGRP_PCC1, 112 PMUX_PINGRP_PBB0, 113 PMUX_PINGRP_CAM_I2C_SCL_PBB1, 114 PMUX_PINGRP_CAM_I2C_SDA_PBB2, 115 PMUX_PINGRP_PBB3, 116 PMUX_PINGRP_PBB4, 117 PMUX_PINGRP_PBB5, 118 PMUX_PINGRP_PBB6, 119 PMUX_PINGRP_PBB7, 120 PMUX_PINGRP_PCC2, 121 PMUX_PINGRP_JTAG_RTCK, 122 PMUX_PINGRP_PWR_I2C_SCL_PZ6, 123 PMUX_PINGRP_PWR_I2C_SDA_PZ7, 124 PMUX_PINGRP_KB_ROW0_PR0, 125 PMUX_PINGRP_KB_ROW1_PR1, 126 PMUX_PINGRP_KB_ROW2_PR2, 127 PMUX_PINGRP_KB_ROW3_PR3, 128 PMUX_PINGRP_KB_ROW4_PR4, 129 PMUX_PINGRP_KB_ROW5_PR5, 130 PMUX_PINGRP_KB_ROW6_PR6, 131 PMUX_PINGRP_KB_ROW7_PR7, 132 PMUX_PINGRP_KB_ROW8_PS0, 133 PMUX_PINGRP_KB_ROW9_PS1, 134 PMUX_PINGRP_KB_ROW10_PS2, 135 PMUX_PINGRP_KB_ROW11_PS3, 136 PMUX_PINGRP_KB_ROW12_PS4, 137 PMUX_PINGRP_KB_ROW13_PS5, 138 PMUX_PINGRP_KB_ROW14_PS6, 139 PMUX_PINGRP_KB_ROW15_PS7, 140 PMUX_PINGRP_KB_COL0_PQ0, 141 PMUX_PINGRP_KB_COL1_PQ1, 142 PMUX_PINGRP_KB_COL2_PQ2, 143 PMUX_PINGRP_KB_COL3_PQ3, 144 PMUX_PINGRP_KB_COL4_PQ4, 145 PMUX_PINGRP_KB_COL5_PQ5, 146 PMUX_PINGRP_KB_COL6_PQ6, 147 PMUX_PINGRP_KB_COL7_PQ7, 148 PMUX_PINGRP_CLK_32K_OUT_PA0, 149 PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4), 150 PMUX_PINGRP_CPU_PWR_REQ, 151 PMUX_PINGRP_PWR_INT_N, 152 PMUX_PINGRP_CLK_32K_IN, 153 PMUX_PINGRP_OWR, 154 PMUX_PINGRP_DAP1_FS_PN0, 155 PMUX_PINGRP_DAP1_DIN_PN1, 156 PMUX_PINGRP_DAP1_DOUT_PN2, 157 PMUX_PINGRP_DAP1_SCLK_PN3, 158 PMUX_PINGRP_DAP_MCLK1_REQ_PEE2, 159 PMUX_PINGRP_DAP_MCLK1_PW4, 160 PMUX_PINGRP_SPDIF_IN_PK6, 161 PMUX_PINGRP_SPDIF_OUT_PK5, 162 PMUX_PINGRP_DAP2_FS_PA2, 163 PMUX_PINGRP_DAP2_DIN_PA4, 164 PMUX_PINGRP_DAP2_DOUT_PA5, 165 PMUX_PINGRP_DAP2_SCLK_PA3, 166 PMUX_PINGRP_DVFS_PWM_PX0, 167 PMUX_PINGRP_GPIO_X1_AUD_PX1, 168 PMUX_PINGRP_GPIO_X3_AUD_PX3, 169 PMUX_PINGRP_DVFS_CLK_PX2, 170 PMUX_PINGRP_GPIO_X4_AUD_PX4, 171 PMUX_PINGRP_GPIO_X5_AUD_PX5, 172 PMUX_PINGRP_GPIO_X6_AUD_PX6, 173 PMUX_PINGRP_GPIO_X7_AUD_PX7, 174 PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), 175 PMUX_PINGRP_SDMMC3_CMD_PA7, 176 PMUX_PINGRP_SDMMC3_DAT0_PB7, 177 PMUX_PINGRP_SDMMC3_DAT1_PB6, 178 PMUX_PINGRP_SDMMC3_DAT2_PB5, 179 PMUX_PINGRP_SDMMC3_DAT3_PB4, 180 PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4), 181 PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, 182 PMUX_PINGRP_PEX_WAKE_N_PDD3, 183 PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4), 184 PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, 185 PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), 186 PMUX_PINGRP_SDMMC1_WP_N_PV3, 187 PMUX_PINGRP_SDMMC3_CD_N_PV2, 188 PMUX_PINGRP_GPIO_W2_AUD_PW2, 189 PMUX_PINGRP_GPIO_W3_AUD_PW3, 190 PMUX_PINGRP_USB_VBUS_EN0_PN4, 191 PMUX_PINGRP_USB_VBUS_EN1_PN5, 192 PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, 193 PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, 194 PMUX_PINGRP_GMI_CLK_LB, 195 PMUX_PINGRP_RESET_OUT_N, 196 PMUX_PINGRP_KB_ROW16_PT0, 197 PMUX_PINGRP_KB_ROW17_PT1, 198 PMUX_PINGRP_USB_VBUS_EN2_PFF1, 199 PMUX_PINGRP_PFF2, 200 PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4), 201 PMUX_PINGRP_COUNT, 202 }; 203 204 enum pmux_drvgrp { 205 PMUX_DRVGRP_AO1, 206 PMUX_DRVGRP_AO2, 207 PMUX_DRVGRP_AT1, 208 PMUX_DRVGRP_AT2, 209 PMUX_DRVGRP_AT3, 210 PMUX_DRVGRP_AT4, 211 PMUX_DRVGRP_AT5, 212 PMUX_DRVGRP_CDEV1, 213 PMUX_DRVGRP_CDEV2, 214 PMUX_DRVGRP_DAP1 = (0x28 / 4), 215 PMUX_DRVGRP_DAP2, 216 PMUX_DRVGRP_DAP3, 217 PMUX_DRVGRP_DAP4, 218 PMUX_DRVGRP_DBG, 219 PMUX_DRVGRP_SDIO3 = (0x48 / 4), 220 PMUX_DRVGRP_SPI, 221 PMUX_DRVGRP_UAA, 222 PMUX_DRVGRP_UAB, 223 PMUX_DRVGRP_UART2, 224 PMUX_DRVGRP_UART3, 225 PMUX_DRVGRP_SDIO1 = (0x84 / 4), 226 PMUX_DRVGRP_DDC = (0x94 / 4), 227 PMUX_DRVGRP_GMA, 228 PMUX_DRVGRP_GME = (0xa8 / 4), 229 PMUX_DRVGRP_GMF, 230 PMUX_DRVGRP_GMG, 231 PMUX_DRVGRP_GMH, 232 PMUX_DRVGRP_OWR, 233 PMUX_DRVGRP_UDA, 234 PMUX_DRVGRP_GPV, 235 PMUX_DRVGRP_DEV3, 236 PMUX_DRVGRP_CEC = (0xd0 / 4), 237 PMUX_DRVGRP_AT6 = (0x12c / 4), 238 PMUX_DRVGRP_DAP5, 239 PMUX_DRVGRP_USB_VBUS_EN, 240 PMUX_DRVGRP_AO3 = (0x140 / 4), 241 PMUX_DRVGRP_AO0 = (0x148 / 4), 242 PMUX_DRVGRP_HV0, 243 PMUX_DRVGRP_SDIO4 = (0x15c / 4), 244 PMUX_DRVGRP_AO4, 245 PMUX_DRVGRP_COUNT, 246 }; 247 248 enum pmux_mipipadctrlgrp { 249 PMUX_MIPIPADCTRLGRP_DSI_B, 250 PMUX_MIPIPADCTRLGRP_COUNT, 251 }; 252 253 enum pmux_func { 254 PMUX_FUNC_DEFAULT, 255 PMUX_FUNC_BLINK, 256 PMUX_FUNC_CCLA, 257 PMUX_FUNC_CEC, 258 PMUX_FUNC_CLDVFS, 259 PMUX_FUNC_CLK, 260 PMUX_FUNC_CLK12, 261 PMUX_FUNC_CPU, 262 PMUX_FUNC_CSI, 263 PMUX_FUNC_DAP, 264 PMUX_FUNC_DAP1, 265 PMUX_FUNC_DAP2, 266 PMUX_FUNC_DEV3, 267 PMUX_FUNC_DISPLAYA, 268 PMUX_FUNC_DISPLAYA_ALT, 269 PMUX_FUNC_DISPLAYB, 270 PMUX_FUNC_DP, 271 PMUX_FUNC_DSI_B, 272 PMUX_FUNC_DTV, 273 PMUX_FUNC_EXTPERIPH1, 274 PMUX_FUNC_EXTPERIPH2, 275 PMUX_FUNC_EXTPERIPH3, 276 PMUX_FUNC_GMI, 277 PMUX_FUNC_GMI_ALT, 278 PMUX_FUNC_HDA, 279 PMUX_FUNC_HSI, 280 PMUX_FUNC_I2C1, 281 PMUX_FUNC_I2C2, 282 PMUX_FUNC_I2C3, 283 PMUX_FUNC_I2C4, 284 PMUX_FUNC_I2CPWR, 285 PMUX_FUNC_I2S0, 286 PMUX_FUNC_I2S1, 287 PMUX_FUNC_I2S2, 288 PMUX_FUNC_I2S3, 289 PMUX_FUNC_I2S4, 290 PMUX_FUNC_IRDA, 291 PMUX_FUNC_KBC, 292 PMUX_FUNC_OWR, 293 PMUX_FUNC_PE, 294 PMUX_FUNC_PE0, 295 PMUX_FUNC_PE1, 296 PMUX_FUNC_PMI, 297 PMUX_FUNC_PWM0, 298 PMUX_FUNC_PWM1, 299 PMUX_FUNC_PWM2, 300 PMUX_FUNC_PWM3, 301 PMUX_FUNC_PWRON, 302 PMUX_FUNC_RESET_OUT_N, 303 PMUX_FUNC_RTCK, 304 PMUX_FUNC_SATA, 305 PMUX_FUNC_SDMMC1, 306 PMUX_FUNC_SDMMC2, 307 PMUX_FUNC_SDMMC3, 308 PMUX_FUNC_SDMMC4, 309 PMUX_FUNC_SOC, 310 PMUX_FUNC_SPDIF, 311 PMUX_FUNC_SPI1, 312 PMUX_FUNC_SPI2, 313 PMUX_FUNC_SPI3, 314 PMUX_FUNC_SPI4, 315 PMUX_FUNC_SPI5, 316 PMUX_FUNC_SPI6, 317 PMUX_FUNC_SYS, 318 PMUX_FUNC_TMDS, 319 PMUX_FUNC_TRACE, 320 PMUX_FUNC_UARTA, 321 PMUX_FUNC_UARTB, 322 PMUX_FUNC_UARTC, 323 PMUX_FUNC_UARTD, 324 PMUX_FUNC_ULPI, 325 PMUX_FUNC_USB, 326 PMUX_FUNC_VGP1, 327 PMUX_FUNC_VGP2, 328 PMUX_FUNC_VGP3, 329 PMUX_FUNC_VGP4, 330 PMUX_FUNC_VGP5, 331 PMUX_FUNC_VGP6, 332 PMUX_FUNC_VI, 333 PMUX_FUNC_VI_ALT1, 334 PMUX_FUNC_VI_ALT3, 335 PMUX_FUNC_VIMCLK2, 336 PMUX_FUNC_VIMCLK2_ALT, 337 PMUX_FUNC_RSVD1, 338 PMUX_FUNC_RSVD2, 339 PMUX_FUNC_RSVD3, 340 PMUX_FUNC_RSVD4, 341 PMUX_FUNC_COUNT, 342 }; 343 344 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 345 #define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 346 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING 347 #define TEGRA_PMX_SOC_HAS_DRVGRPS 348 #define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS 349 #define TEGRA_PMX_GRPS_HAVE_LPMD 350 #define TEGRA_PMX_GRPS_HAVE_SCHMT 351 #define TEGRA_PMX_GRPS_HAVE_HSM 352 #define TEGRA_PMX_PINS_HAVE_E_INPUT 353 #define TEGRA_PMX_PINS_HAVE_LOCK 354 #define TEGRA_PMX_PINS_HAVE_OD 355 #define TEGRA_PMX_PINS_HAVE_IO_RESET 356 #define TEGRA_PMX_PINS_HAVE_RCV_SEL 357 #include <asm/arch-tegra/pinmux.h> 358 359 #endif /* _TEGRA124_PINMUX_H_ */ 360
