1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 * Author: Jason Jin<Jason.jin (at) freescale.com> 5 * Zhang Wei<wei.zhang (at) freescale.com> 6 */ 7 #ifndef _AHCI_H_ 8 #define _AHCI_H_ 9 10 #include <pci.h> 11 12 #define AHCI_PCI_BAR 0x24 13 #define AHCI_MAX_SG 56 /* hardware max is 64K */ 14 #define AHCI_CMD_SLOT_SZ 32 15 #define AHCI_MAX_CMD_SLOT 32 16 #define AHCI_RX_FIS_SZ 256 17 #define AHCI_CMD_TBL_HDR 0x80 18 #define AHCI_CMD_TBL_CDB 0x40 19 #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) 20 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ 21 AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) 22 #define AHCI_CMD_ATAPI (1 << 5) 23 #define AHCI_CMD_WRITE (1 << 6) 24 #define AHCI_CMD_PREFETCH (1 << 7) 25 #define AHCI_CMD_RESET (1 << 8) 26 #define AHCI_CMD_CLR_BUSY (1 << 10) 27 28 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 29 30 /* Global controller registers */ 31 #define HOST_CAP 0x00 /* host capabilities */ 32 #define HOST_CTL 0x04 /* global host control */ 33 #define HOST_IRQ_STAT 0x08 /* interrupt status */ 34 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 35 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 36 #define HOST_CAP2 0x24 /* host capabilities, extended */ 37 38 /* HOST_CTL bits */ 39 #define HOST_RESET (1 << 0) /* reset controller; self-clear */ 40 #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ 41 #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ 42 43 /* Registers for each SATA port */ 44 #define PORT_LST_ADDR 0x00 /* command list DMA addr */ 45 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ 46 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ 47 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ 48 #define PORT_IRQ_STAT 0x10 /* interrupt status */ 49 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ 50 #define PORT_CMD 0x18 /* port command */ 51 #define PORT_TFDATA 0x20 /* taskfile data */ 52 #define PORT_SIG 0x24 /* device TF signature */ 53 #define PORT_CMD_ISSUE 0x38 /* command issue */ 54 #define PORT_SCR 0x28 /* SATA phy register block */ 55 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ 56 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ 57 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ 58 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ 59 60 #ifdef CONFIG_SUNXI_AHCI 61 #define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */ 62 #endif 63 64 /* PORT_IRQ_{STAT,MASK} bits */ 65 #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ 66 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 67 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 68 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 69 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 70 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 71 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 72 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 73 74 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 75 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 76 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 77 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 78 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 79 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 80 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 81 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 82 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 83 84 #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ 85 | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR 86 87 #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ 88 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ 89 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ 90 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ 91 | PORT_IRQ_D2H_REG_FIS 92 93 /* PORT_SCR_STAT bits */ 94 #define PORT_SCR_STAT_DET_MASK 0x3 95 #define PORT_SCR_STAT_DET_COMINIT 0x1 96 #define PORT_SCR_STAT_DET_PHYRDY 0x3 97 98 /* PORT_CMD bits */ 99 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 100 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 101 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 102 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 103 #define PORT_CMD_CLO (1 << 3) /* Command list override */ 104 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 105 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 106 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 107 108 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 109 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 110 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 111 112 #define AHCI_MAX_PORTS 32 113 114 #define ATA_FLAG_SATA (1 << 3) 115 #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ 116 #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ 117 #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ 118 #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ 119 #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ 120 121 struct ahci_cmd_hdr { 122 u32 opts; 123 u32 status; 124 u32 tbl_addr; 125 u32 tbl_addr_hi; 126 u32 reserved[4]; 127 }; 128 129 struct ahci_sg { 130 u32 addr; 131 u32 addr_hi; 132 u32 reserved; 133 u32 flags_size; 134 }; 135 136 struct ahci_ioports { 137 void __iomem *cmd_addr; 138 void __iomem *scr_addr; 139 void __iomem *port_mmio; 140 struct ahci_cmd_hdr *cmd_slot; 141 struct ahci_sg *cmd_tbl_sg; 142 ulong cmd_tbl; 143 u32 rx_fis; 144 }; 145 146 /** 147 * struct ahci_uc_priv - information about an AHCI controller 148 * 149 * When driver model is used, this is accessible using dev_get_uclass_priv(dev) 150 * where dev is the controller (although at present it sometimes stands alone). 151 */ 152 struct ahci_uc_priv { 153 #if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 154 /* 155 * TODO(sjg (at) chromium.org): Drop this once this structure is only used 156 * in a driver-model context (i.e. attached to a device with 157 * dev_get_uclass_priv() 158 */ 159 struct udevice *dev; 160 #else 161 pci_dev_t dev; 162 #endif 163 struct ahci_ioports port[AHCI_MAX_PORTS]; 164 u16 *ataid[AHCI_MAX_PORTS]; 165 u32 n_ports; 166 u32 hard_port_no; 167 u32 host_flags; 168 u32 host_set_flags; 169 void __iomem *mmio_base; 170 u32 pio_mask; 171 u32 udma_mask; 172 u32 flags; 173 u32 cap; /* cache of HOST_CAP register */ 174 u32 port_map; /* cache of HOST_PORTS_IMPL reg */ 175 u32 link_port_map; /*linkup port map*/ 176 }; 177 178 struct ahci_ops { 179 /** 180 * reset() - reset the controller 181 * 182 * @dev: Controller to reset 183 * @return 0 if OK, -ve on error 184 */ 185 int (*reset)(struct udevice *dev); 186 187 /** 188 * port_status() - get the status of a SATA port 189 * 190 * @dev: Controller to reset 191 * @port: Port number to check (0 for first) 192 * @return 0 if detected, -ENXIO if nothing on port, other -ve on error 193 */ 194 int (*port_status)(struct udevice *dev, int port); 195 196 /** 197 * scan() - scan SATA ports 198 * 199 * @dev: Controller to scan 200 * @return 0 if OK, -ve on error 201 */ 202 int (*scan)(struct udevice *dev); 203 }; 204 205 #define ahci_get_ops(dev) ((struct ahci_ops *)(dev)->driver->ops) 206 207 /** 208 * sata_reset() - reset the controller 209 * 210 * @dev: Controller to reset 211 * @return 0 if OK, -ve on error 212 */ 213 int sata_reset(struct udevice *dev); 214 215 /** 216 * sata_port_status() - get the status of a SATA port 217 * 218 * @dev: Controller to reset 219 * @port: Port number to check (0 for first) 220 * @return 0 if detected, -ENXIO if nothin on port, other -ve on error 221 */ 222 int sata_dm_port_status(struct udevice *dev, int port); 223 224 /** 225 * sata_scan() - scan SATA ports 226 * 227 * @dev: Controller to scan 228 * @return 0 if OK, -ve on error 229 */ 230 int sata_scan(struct udevice *dev); 231 232 int ahci_init(void __iomem *base); 233 int ahci_reset(void __iomem *base); 234 235 /** 236 * ahci_init_one_dm() - set up a single AHCI port 237 * 238 * @dev: Controller to init 239 */ 240 int ahci_init_one_dm(struct udevice *dev); 241 242 /** 243 * ahci_start_ports_dm() - start all AHCI ports for a controller 244 * 245 * @dev: Controller containing ports to start 246 */ 247 int ahci_start_ports_dm(struct udevice *dev); 248 249 /** 250 * ahci_init_dm() - init AHCI for a controller, finding all ports 251 * 252 * @dev: Device to init 253 */ 254 int ahci_init_dm(struct udevice *dev, void __iomem *base); 255 256 /** 257 * ahci_bind_scsi() - bind a new SCSI bus as a child 258 * 259 * Note that the SCSI bus device will itself bind block devices 260 * 261 * @ahci_dev: AHCI parent device 262 * @devp: Returns new SCSI bus device 263 * @return 0 if OK, -ve on error 264 */ 265 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp); 266 267 /** 268 * ahci_probe_scsi() - probe and scan the attached SCSI bus 269 * 270 * Note that the SCSI device will itself bind block devices for any storage 271 * devices it finds. 272 * 273 * @ahci_dev: AHCI parent device 274 * @base: Base address of AHCI port 275 * @return 0 if OK, -ve on error 276 */ 277 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base); 278 279 /** 280 * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI 281 * 282 * Note that the SCSI device will itself bind block devices for any storage 283 * devices it finds. 284 * 285 * @ahci_dev: AHCI parent device 286 * @return 0 if OK, -ve on error 287 */ 288 int ahci_probe_scsi_pci(struct udevice *ahci_dev); 289 290 #endif 291
