1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 4 * Author: Shawn Lin <shawn.lin (at) rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 9 10 /* pll id */ 11 #define PLL_APLL 0 12 #define PLL_DPLL 1 13 #define PLL_GPLL 2 14 #define ARMCLK 3 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_MAC 64 18 #define SCLK_SPI0 65 19 #define SCLK_NANDC 67 20 #define SCLK_SDMMC 68 21 #define SCLK_SDIO 69 22 #define SCLK_EMMC 71 23 #define SCLK_UART0 72 24 #define SCLK_UART1 73 25 #define SCLK_UART2 74 26 #define SCLK_I2S0 75 27 #define SCLK_I2S1 76 28 #define SCLK_I2S2 77 29 #define SCLK_TIMER0 78 30 #define SCLK_TIMER1 79 31 #define SCLK_SFC 80 32 #define SCLK_SDMMC_DRV 81 33 #define SCLK_SDIO_DRV 82 34 #define SCLK_EMMC_DRV 83 35 #define SCLK_SDMMC_SAMPLE 84 36 #define SCLK_SDIO_SAMPLE 85 37 #define SCLK_EMMC_SAMPLE 86 38 #define SCLK_MAC_RX 87 39 #define SCLK_MAC_TX 88 40 #define SCLK_MACREF 89 41 #define SCLK_MACREF_OUT 90 42 #define SCLK_SARADC 91 43 44 45 /* aclk gates */ 46 #define ACLK_DMAC 192 47 #define ACLK_PRE 193 48 #define ACLK_CORE 194 49 #define ACLK_ENMCORE 195 50 #define ACLK_GMAC 196 51 52 53 /* pclk gates */ 54 #define PCLK_GPIO1 256 55 #define PCLK_GPIO2 257 56 #define PCLK_GPIO3 258 57 #define PCLK_GRF 259 58 #define PCLK_I2C1 260 59 #define PCLK_I2C2 261 60 #define PCLK_I2C3 262 61 #define PCLK_SPI 263 62 #define PCLK_SFC 264 63 #define PCLK_UART0 265 64 #define PCLK_UART1 266 65 #define PCLK_UART2 267 66 #define PCLK_TSADC 268 67 #define PCLK_PWM 269 68 #define PCLK_TIMER 270 69 #define PCLK_PERI 271 70 #define PCLK_GMAC 272 71 #define PCLK_SARADC 273 72 73 /* hclk gates */ 74 #define HCLK_I2S0_8CH 320 75 #define HCLK_I2S1_8CH 321 76 #define HCLK_I2S2_2CH 322 77 #define HCLK_NANDC 323 78 #define HCLK_SDMMC 324 79 #define HCLK_SDIO 325 80 #define HCLK_EMMC 326 81 #define HCLK_PERI 327 82 #define HCLK_SFC 328 83 84 #define CLK_NR_CLKS (HCLK_SFC + 1) 85 86 /* reset id */ 87 #define SRST_CORE_PO_AD 0 88 #define SRST_CORE_AD 1 89 #define SRST_L2_AD 2 90 #define SRST_CPU_NIU_AD 3 91 #define SRST_CORE_PO 4 92 #define SRST_CORE 5 93 #define SRST_L2 6 94 #define SRST_CORE_DBG 8 95 #define PRST_DBG 9 96 #define RST_DAP 10 97 #define PRST_DBG_NIU 11 98 #define ARST_STRC_SYS_AD 15 99 100 #define SRST_DDRPHY_CLKDIV 16 101 #define SRST_DDRPHY 17 102 #define PRST_DDRPHY 18 103 #define PRST_HDMIPHY 19 104 #define PRST_VDACPHY 20 105 #define PRST_VADCPHY 21 106 #define PRST_MIPI_CSI_PHY 22 107 #define PRST_MIPI_DSI_PHY 23 108 #define PRST_ACODEC 24 109 #define ARST_BUS_NIU 25 110 #define PRST_TOP_NIU 26 111 #define ARST_INTMEM 27 112 #define HRST_ROM 28 113 #define ARST_DMAC 29 114 #define SRST_MSCH_NIU 30 115 #define PRST_MSCH_NIU 31 116 117 #define PRST_DDRUPCTL 32 118 #define NRST_DDRUPCTL 33 119 #define PRST_DDRMON 34 120 #define HRST_I2S0_8CH 35 121 #define MRST_I2S0_8CH 36 122 #define HRST_I2S1_2CH 37 123 #define MRST_IS21_2CH 38 124 #define HRST_I2S2_2CH 39 125 #define MRST_I2S2_2CH 40 126 #define HRST_CRYPTO 41 127 #define SRST_CRYPTO 42 128 #define PRST_SPI 43 129 #define SRST_SPI 44 130 #define PRST_UART0 45 131 #define PRST_UART1 46 132 #define PRST_UART2 47 133 134 #define SRST_UART0 48 135 #define SRST_UART1 49 136 #define SRST_UART2 50 137 #define PRST_I2C1 51 138 #define PRST_I2C2 52 139 #define PRST_I2C3 53 140 #define SRST_I2C1 54 141 #define SRST_I2C2 55 142 #define SRST_I2C3 56 143 #define PRST_PWM1 58 144 #define SRST_PWM1 60 145 #define PRST_WDT 61 146 #define PRST_GPIO1 62 147 #define PRST_GPIO2 63 148 149 #define PRST_GPIO3 64 150 #define PRST_GRF 65 151 #define PRST_EFUSE 66 152 #define PRST_EFUSE512 67 153 #define PRST_TIMER0 68 154 #define SRST_TIMER0 69 155 #define SRST_TIMER1 70 156 #define PRST_TSADC 71 157 #define SRST_TSADC 72 158 #define PRST_SARADC 73 159 #define SRST_SARADC 74 160 #define HRST_SYSBUS 75 161 #define PRST_USBGRF 76 162 163 #define ARST_PERIPH_NIU 80 164 #define HRST_PERIPH_NIU 81 165 #define PRST_PERIPH_NIU 82 166 #define HRST_PERIPH 83 167 #define HRST_SDMMC 84 168 #define HRST_SDIO 85 169 #define HRST_EMMC 86 170 #define HRST_NANDC 87 171 #define NRST_NANDC 88 172 #define HRST_SFC 89 173 #define SRST_SFC 90 174 #define ARST_GMAC 91 175 #define HRST_OTG 92 176 #define SRST_OTG 93 177 #define SRST_OTG_ADP 94 178 #define HRST_HOST0 95 179 180 #define HRST_HOST0_AUX 96 181 #define HRST_HOST0_ARB 97 182 #define SRST_HOST0_EHCIPHY 98 183 #define SRST_HOST0_UTMI 99 184 #define SRST_USBPOR 100 185 #define SRST_UTMI0 101 186 #define SRST_UTMI1 102 187 188 #define ARST_VIO0_NIU 102 189 #define ARST_VIO1_NIU 103 190 #define HRST_VIO_NIU 104 191 #define PRST_VIO_NIU 105 192 #define ARST_VOP 106 193 #define HRST_VOP 107 194 #define DRST_VOP 108 195 #define ARST_IEP 109 196 #define HRST_IEP 110 197 #define ARST_RGA 111 198 #define HRST_RGA 112 199 #define SRST_RGA 113 200 #define PRST_CVBS 114 201 #define PRST_HDMI 115 202 #define SRST_HDMI 116 203 #define PRST_MIPI_DSI 117 204 205 #define ARST_ISP_NIU 118 206 #define HRST_ISP_NIU 119 207 #define HRST_ISP 120 208 #define SRST_ISP 121 209 #define ARST_VIP0 122 210 #define HRST_VIP0 123 211 #define PRST_VIP0 124 212 #define ARST_VIP1 125 213 #define HRST_VIP1 126 214 #define PRST_VIP1 127 215 #define ARST_VIP2 128 216 #define HRST_VIP2 129 217 #define PRST_VIP2 120 218 #define ARST_VIP3 121 219 #define HRST_VIP3 122 220 #define PRST_VIP4 123 221 222 #define PRST_CIF1TO4 124 223 #define SRST_CVBS_CLK 125 224 #define HRST_CVBS 126 225 226 #define ARST_VPU_NIU 140 227 #define HRST_VPU_NIU 141 228 #define ARST_VPU 142 229 #define HRST_VPU 143 230 #define ARST_RKVDEC_NIU 144 231 #define HRST_RKVDEC_NIU 145 232 #define ARST_RKVDEC 146 233 #define HRST_RKVDEC 147 234 #define SRST_RKVDEC_CABAC 148 235 #define SRST_RKVDEC_CORE 149 236 #define ARST_RKVENC_NIU 150 237 #define HRST_RKVENC_NIU 151 238 #define ARST_RKVENC 152 239 #define HRST_RKVENC 153 240 #define SRST_RKVENC_CORE 154 241 242 #define SRST_DSP_CORE 156 243 #define SRST_DSP_SYS 157 244 #define SRST_DSP_GLOBAL 158 245 #define SRST_DSP_OECM 159 246 #define PRST_DSP_IOP_NIU 160 247 #define ARST_DSP_EPP_NIU 161 248 #define ARST_DSP_EDP_NIU 162 249 #define PRST_DSP_DBG_NIU 163 250 #define PRST_DSP_CFG_NIU 164 251 #define PRST_DSP_GRF 165 252 #define PRST_DSP_MAILBOX 166 253 #define PRST_DSP_INTC 167 254 #define PRST_DSP_PFM_MON 169 255 #define SRST_DSP_PFM_MON 170 256 #define ARST_DSP_EDAP_NIU 171 257 258 #define SRST_PMU 172 259 #define SRST_PMU_I2C0 173 260 #define PRST_PMU_I2C0 174 261 #define PRST_PMU_GPIO0 175 262 #define PRST_PMU_INTMEM 176 263 #define PRST_PMU_PWM0 177 264 #define SRST_PMU_PWM0 178 265 #define PRST_PMU_GRF 179 266 #define SRST_PMU_NIU 180 267 #define SRST_PMU_PVTM 181 268 #define ARST_DSP_EDP_PERF 184 269 #define ARST_DSP_EPP_PERF 185 270 271 #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 272
