1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * David Feng <fenghua (at) phytium.com.cn> 5 */ 6 7 #ifndef _ASM_ARMV8_MMU_H_ 8 #define _ASM_ARMV8_MMU_H_ 9 10 /* 11 * block/section address mask and size definitions. 12 */ 13 14 /* PAGE_SHIFT determines the page size */ 15 #undef PAGE_SIZE 16 #define PAGE_SHIFT 12 17 #define PAGE_SIZE (1 << PAGE_SHIFT) 18 #define PAGE_MASK (~(PAGE_SIZE - 1)) 19 20 /***************************************************************/ 21 22 /* 23 * Memory types 24 */ 25 #define MT_DEVICE_NGNRNE 0 26 #define MT_DEVICE_NGNRE 1 27 #define MT_DEVICE_GRE 2 28 #define MT_NORMAL_NC 3 29 #define MT_NORMAL 4 30 31 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ 32 (0x04 << (MT_DEVICE_NGNRE * 8)) | \ 33 (0x0c << (MT_DEVICE_GRE * 8)) | \ 34 (0x44 << (MT_NORMAL_NC * 8)) | \ 35 (UL(0xff) << (MT_NORMAL * 8))) 36 37 /* 38 * Hardware page table definitions. 39 * 40 */ 41 42 #define PTE_TYPE_MASK (3 << 0) 43 #define PTE_TYPE_FAULT (0 << 0) 44 #define PTE_TYPE_TABLE (3 << 0) 45 #define PTE_TYPE_PAGE (3 << 0) 46 #define PTE_TYPE_BLOCK (1 << 0) 47 #define PTE_TYPE_VALID (1 << 0) 48 49 #define PTE_TABLE_PXN (1UL << 59) 50 #define PTE_TABLE_XN (1UL << 60) 51 #define PTE_TABLE_AP (1UL << 61) 52 #define PTE_TABLE_NS (1UL << 63) 53 54 /* 55 * Block 56 */ 57 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2) 58 #define PTE_BLOCK_NS (1 << 5) 59 #define PTE_BLOCK_NON_SHARE (0 << 8) 60 #define PTE_BLOCK_OUTER_SHARE (2 << 8) 61 #define PTE_BLOCK_INNER_SHARE (3 << 8) 62 #define PTE_BLOCK_AF (1 << 10) 63 #define PTE_BLOCK_NG (1 << 11) 64 #define PTE_BLOCK_PXN (UL(1) << 53) 65 #define PTE_BLOCK_UXN (UL(1) << 54) 66 67 /* 68 * AttrIndx[2:0] 69 */ 70 #define PMD_ATTRINDX(t) ((t) << 2) 71 #define PMD_ATTRINDX_MASK (7 << 2) 72 #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ 73 PTE_BLOCK_UXN | \ 74 PMD_ATTRINDX_MASK | \ 75 PTE_TYPE_VALID) 76 77 /* 78 * TCR flags. 79 */ 80 #define TCR_T0SZ(x) ((64 - (x)) << 0) 81 #define TCR_IRGN_NC (0 << 8) 82 #define TCR_IRGN_WBWA (1 << 8) 83 #define TCR_IRGN_WT (2 << 8) 84 #define TCR_IRGN_WBNWA (3 << 8) 85 #define TCR_IRGN_MASK (3 << 8) 86 #define TCR_ORGN_NC (0 << 10) 87 #define TCR_ORGN_WBWA (1 << 10) 88 #define TCR_ORGN_WT (2 << 10) 89 #define TCR_ORGN_WBNWA (3 << 10) 90 #define TCR_ORGN_MASK (3 << 10) 91 #define TCR_SHARED_NON (0 << 12) 92 #define TCR_SHARED_OUTER (2 << 12) 93 #define TCR_SHARED_INNER (3 << 12) 94 #define TCR_TG0_4K (0 << 14) 95 #define TCR_TG0_64K (1 << 14) 96 #define TCR_TG0_16K (2 << 14) 97 #define TCR_EPD1_DISABLE (1 << 23) 98 99 #define TCR_EL1_RSVD (1 << 31) 100 #define TCR_EL2_RSVD (1 << 31 | 1 << 23) 101 #define TCR_EL3_RSVD (1 << 31 | 1 << 23) 102 103 #ifndef __ASSEMBLY__ 104 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) 105 { 106 asm volatile("dsb sy"); 107 if (el == 1) { 108 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); 109 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); 110 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); 111 } else if (el == 2) { 112 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); 113 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); 114 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); 115 } else if (el == 3) { 116 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); 117 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); 118 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); 119 } else { 120 hang(); 121 } 122 asm volatile("isb"); 123 } 124 125 struct mm_region { 126 u64 virt; 127 u64 phys; 128 u64 size; 129 u64 attrs; 130 }; 131 132 extern struct mm_region *mem_map; 133 void setup_pgtables(void); 134 u64 get_tcr(int el, u64 *pips, u64 *pva_bits); 135 #endif 136 137 #endif /* _ASM_ARMV8_MMU_H_ */ 138
