| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/ |
| SmbusPolicy.h | 39 UINT32 PciAddress;
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSmm/ |
| S3Save.c | 91 SMM_PCI_IO_ADDRESS PciAddress;
267 PciAddress.Bus = 0;
268 PciAddress.Device = 0;
269 PciAddress.Function = 0;
270 PciAddress.ExtendedRegister = 0;
276 PciAddress.Register = ExtReg[Index];
279 PciAddress.Bus,
280 PciAddress.Device,
281 PciAddress.Function,
282 PciAddress.Register
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/Ia32/ |
| PlatformIoLib.c | 47 PciAddress to be written to Config Port
86 UINT32 PciAddress;
90 PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
94 PciAddress1 = PciAddress;
95 PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
97 Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
132 UINT32 PciAddress;
136 PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
140 PciAddress1 = PciAddress;
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/X64/ |
| PlatformIoLib.c | 47 PciAddress to be written to Config Port
88 UINT32 PciAddress;
92 PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
96 PciAddress1 = PciAddress;
97 PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
99 Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
134 UINT32 PciAddress;
138 PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
142 PciAddress1 = PciAddress;
[all...] |
| /device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/PciHostBridgeLib/ |
| PciHostBridgeSupport.c | 124 UINTN PciAddress;
126 PciAddress = (UINTN)Address;
131 *OriginalValue = PciRead32 (PciAddress);
138 PciWrite32 (PciAddress, 0xFFFFFFFF);
139 *Value = PciRead32 (PciAddress);
140 PciWrite32 (PciAddress, *OriginalValue);
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Dxe/Include/ |
| EfiRegTableLib.h | 77 UINT32 PciAddress;
91 UINT32 PciAddress;
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/ |
| PciHotPlugSupport.c | 420 UINT64 PciAddress;
428 PciAddress = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
432 PciAddress,
|
| PciLib.c | 986 UINT64 PciAddress;
1002 PciAddress = 0;
[all...] |
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/ |
| PciRootBridge.h | 85 UINTN PciAddress;
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Library/ |
| EfiRegTableLib.h | 86 UINT32 PciAddress;
106 UINT32 PciAddress;
|
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/ |
| PcatIo.c | 101 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;
127 CopyMem (&PciAddress, &UserAddress, sizeof(UINT64));
129 if (PciAddress.ExtendedRegister > 0xFF) {
140 if (PciAddress.ExtendedRegister != 0) {
141 Pci.Bits.Reg = PciAddress.ExtendedRegister & 0xFF;
143 Pci.Bits.Reg = PciAddress.Register;
151 Pci.Bits.Func = PciAddress.Function;
152 Pci.Bits.Dev = PciAddress.Device;
153 Pci.Bits.Bus = PciAddress.Bus;
172 This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned);
[all...] |
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/ |
| PcatPciRootBridge.h | 69 UINT64 PciAddress;
|
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/ |
| PcatIo.c | 101 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;
127 CopyMem (&PciAddress, &UserAddress, sizeof(UINT64));
129 if (PciAddress.ExtendedRegister > 0xFF) {
140 if (PciAddress.ExtendedRegister != 0) {
141 Pci.Bits.Reg = PciAddress.ExtendedRegister & 0xFF;
143 Pci.Bits.Reg = PciAddress.Register;
151 Pci.Bits.Func = PciAddress.Function;
152 Pci.Bits.Dev = PciAddress.Device;
153 Pci.Bits.Bus = PciAddress.Bus;
172 This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned);
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/ |
| PciRootBridgeIo.c | [all...] |
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/ |
| AcpiPciUpdate.c | 231 @param PciAddress Pci address from VPD
237 IN UINT32 PciAddress
242 ReturnAddress = ((PciAddress & 0x0000FF00) << 8) | (PciAddress & 0x000000FF);
244 if ((PciAddress & 0x000000FF) == 0x000000FF)
483 @param PciAddress Acpi pci address
495 IN UINT32 PciAddress,
526 if (CurrentPciAddress != PciAddress) {
583 @param PciAddress Acpi pci address
593 IN UINT32 PciAddress,
[all...] |
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/ |
| AcpiSmmPlatform.c | 825 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;
845 PciAddress.Bus = mPciCfgRegTable[Index++];
846 PciAddress.Device = mPciCfgRegTable[Index++];
847 PciAddress.Function = mPciCfgRegTable[Index++];
848 PciAddress.Register = 0;
849 PciAddress.ExtendedRegister = 0;
851 Data16 = PciRead16 (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/ |
| PciHostBridge.h | 373 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
393 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
475 UINTN PciAddress;
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Library/PiDxeS3BootScriptLib/ |
| BootScriptExecute.c | 668 UINT64 PciAddress;
672 PciAddress = PCI_ADDRESS_ENCODE (Segment, Address);
674 Status = BuildLoopData (Width, PciAddress, &AddressStride, &BufferStride);
681 for (; Count > 0; Count--, PciAddress += AddressStride, Out.Buf += BufferStride) {
684 DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint8 - 0x%016lx\n", PciAddress));
685 *Out.Uint8 = PciSegmentRead8 (PciAddress);
688 DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint8 - 0x%016lx\n", PciAddress));
689 *Out.Uint8 = PciSegmentRead8 (PciAddress);
692 DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint8 - 0x%016lx\n", PciAddress));
693 *Out.Uint8 = PciSegmentRead8 (PciAddress);
[all...] |
