| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
108 unsigned PredReg = 0;
109 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
225 ARMCC::CondCodes Pred, unsigned PredReg,
231 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
255 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
264 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
275 .addImm((unsigned)Pred).addReg(PredReg).addReg(0
[all...] |
| MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg();
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 189 unsigned PredReg = 0;
190 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
425 .addImm(0).addImm(Pred).addReg(PredReg)
764 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
772 Offset, Pred, PredReg, TII);
776 Offset, Pred, PredReg, TII);
|
| Thumb2SizeReduction.cpp | 441 unsigned PredReg = MI->getOperand(5).getReg();
454 .addReg(PredReg)
647 unsigned PredReg = 0;
648 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
752 unsigned PredReg = 0;
753 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
848 unsigned PredReg = 0;
849 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
[all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 150 ARMCC::CondCodes Pred, unsigned PredReg);
154 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
159 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
460 unsigned PredReg) {
528 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
546 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
711 .addImm(Pred).addReg(PredReg);
721 .addImm(Pred).addReg(PredReg);
726 .addImm(Pred).addReg(PredReg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 55 unsigned PredReg = 0;
56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
103 unsigned PredReg = 0;
104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
177 ARMCC::CondCodes Pred, unsigned PredReg,
192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
400 unsigned PredReg;
[all...] |
| MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg();
230 MIB.addImm(Pred).addReg(PredReg);
242 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 172 unsigned PredReg = 0;
173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 804 unsigned PredReg, unsigned MIFlags) const {
814 .addImm(0).addImm(Pred).addReg(PredReg)
838 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
841 Pred, PredReg, TII);
844 Pred, PredReg, TII);
877 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
878 unsigned PredReg = Old->getOperand(2).getReg();
879 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
881 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
882 unsigned PredReg = Old->getOperand(3).getReg()
[all...] |
| ARMExpandPseudoInsts.cpp | 647 unsigned PredReg = 0;
648 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
[all...] |
| Thumb2SizeReduction.cpp | 533 unsigned PredReg = 0;
534 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
614 unsigned PredReg = 0;
615 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
705 unsigned PredReg = 0;
706 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 70 unsigned PredReg = 0;
71 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
118 unsigned PredReg = 0;
119 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
240 ARMCC::CondCodes Pred, unsigned PredReg,
246 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
263 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
270 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
279 .add(predOps(Pred, PredReg))
291 .add(predOps(Pred, PredReg))
[all...] |
| MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg();
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 206 unsigned PredReg = 0;
207 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 438 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
450 .add(predOps(Pred, PredReg))
783 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
791 Offset, Pred, PredReg, TII);
795 Offset, Pred, PredReg, TII);
[all...] |
| Thumb2SizeReduction.cpp | 471 unsigned PredReg = MI->getOperand(5).getReg();
484 .addReg(PredReg)
679 unsigned PredReg = 0;
680 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
782 unsigned PredReg = 0;
783 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
875 unsigned PredReg = 0;
876 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
472 PredReg = MCI.getOperand(1).getReg(); // P0
474 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
[all...] |
| HexagonMCChecker.cpp | 58 unsigned PredReg = Hexagon::NoRegister;
68 PredReg = R;
73 NewPreds.insert(PredReg);
112 Defs[R].insert(PredSense(PredReg, isTrue));
156 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue));
169 Defs[*SRI].insert(PredSense(PredReg, isTrue));
185 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
197 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
221 NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));
564 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0)
[all...] |
| HexagonMCCompound.cpp | 182 unsigned PredReg = Predicate.getReg();
184 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
185 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
192 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt;
194 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t;
196 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt;
198 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
|
| HexagonMCChecker.h | 91 /// PredReg = predicate register, 0 if use/def not predicated,
92 /// Cond = true/false for if(PredReg)/if(!PredReg) respectively,
98 unsigned PredReg;
102 NewSense NS = { /*PredReg=*/ 0, /*IsFloat=*/ false, /*IsNVJ=*/ isNVJ,
107 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ false, /*IsNVJ=*/ false,
112 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ Float, /*IsNVJ=*/ false,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 186 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
474 PredReg = MCI.getOperand(1).getReg(); // P0
476 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
[all...] |
| HexagonMCCompound.cpp | 178 unsigned PredReg = Predicate.getReg();
180 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
181 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
188 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt;
190 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t;
192 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt;
194 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
|
| HexagonMCChecker.cpp | 68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
72 PredReg = R;
77 NewPreds.insert(PredReg);
90 unsigned PredReg = Hexagon::NoRegister;
96 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
98 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
126 Defs[R].insert(PredSense(PredReg, isTrue));
178 Defs[*SRI].insert(PredSense(PredReg, isTrue));
|
