1 /* 2 * definitions for MPC8xxx I/O Ports 3 * 4 * Murray.Jensen (at) cmst.csiro.au, 20-Oct-00 5 */ 6 7 /* 8 * this structure mirrors the layout of the five port registers in 9 * the internal memory map 10 */ 11 typedef struct { 12 unsigned int pdir; /* Port Data Direction Register (35-3) */ 13 unsigned int ppar; /* Port Pin Assignment Register (35-4) */ 14 unsigned int psor; /* Port Special Options Register (35-5) */ 15 unsigned int podr; /* Port Open Drain Register (35-2) */ 16 unsigned int pdat; /* Port Data Register (35-3) */ 17 } ioport_t; 18 19 /* 20 * this macro calculates the address within the internal 21 * memory map (im) of the set of registers for a port (idx) 22 * 23 * the internal memory map aligns the above structure on 24 * a 0x20 byte boundary 25 */ 26 #ifdef CONFIG_MPC85xx 27 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) 28 #else 29 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) 30 #endif 31 32 /* 33 * this structure provides configuration 34 * information for one port pin 35 */ 36 typedef struct { 37 unsigned char conf:1; /* if 1, configure this port */ 38 unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */ 39 unsigned char psor:1; /* Port Special Options Register (35-2) */ 40 unsigned char pdir:1; /* Port Data Direction Register (35-3) */ 41 unsigned char podr:1; /* Port Open Drain Register (35-2) */ 42 unsigned char pdat:1; /* Port Data Register (35-2) */ 43 } iop_conf_t; 44 45 /* 46 * a table that contains configuration information for all 32 pins 47 * 48 * NOTE: in the second dimension of this table, index 0 refers to pin 31 49 * and index 31 refers to pin 0. this made the code in the table look more 50 * like the table in the 8260UM (and in the hymod manuals). 51 */ 52 extern const iop_conf_t iop_conf_tab[4][32]; 53 54 typedef struct { 55 unsigned char port; 56 unsigned char pin; 57 int dir; 58 int open_drain; 59 int assign; 60 } qe_iop_conf_t; 61 62 #define QE_IOP_TAB_END (-1) 63
