| /external/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true);
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
|
| LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
61 S2RCMap.insert(std::make_pair(Slot, RC));
65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
78 if (RC)
79 OS << " [" << RC->getName() << "]\n";
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.cpp | 39 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
44 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true);
46 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
47 TRI.getSpillAlignment(RC), true);
57 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
60 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
61 TRI.getSpillAlignment(RC), true);
70 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
73 unsigned Size = TRI.getSpillSize(RC);
74 unsigned Align = TRI.getSpillAlignment(RC);
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBank.cpp | 29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
31 if (!covers(RC))
37 // RegisterBankInfo to find the subclasses of RC, to make sure
42 if (!RC.hasSubClassEq(&SubRC))
55 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
57 return ContainedRegClasses.test(RC.getID());
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
99 if (!covers(RC))
104 OS << TRI->getRegClassName(&RC);
|
| /external/llvm/lib/CodeGen/ |
| LiveStackAnalysis.cpp | 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
66 S2RCMap.insert(std::make_pair(Slot, RC));
70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
83 if (RC)
84 OS << " [" << TRI->getRegClassName(RC) << "]\n";
|
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 41 const TargetRegisterClass *RC =
53 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
58 const TargetRegisterClass *RC =
63 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
64 RC->getAlignment(), false);
73 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
77 RC->getSize(), RC->getAlignment(), false);
96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
99 RC->getSize(), RC->getAlignment(), false)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyReplacePhysRegs.cpp | 83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
89 VReg = MRI.createVirtualRegister(RC);
|
| WebAssemblyInstrInfo.cpp | 58 const TargetRegisterClass *RC =
64 if (RC == &WebAssembly::I32RegClass)
66 else if (RC == &WebAssembly::I64RegClass)
68 else if (RC == &WebAssembly::F32RegClass)
70 else if (RC == &WebAssembly::F64RegClass)
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinFrameLowering.cpp | 122 const TargetRegisterClass *RC = BF::DPRegisterClass;
126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
127 RC->getAlignment(),
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| TargetRegisterInfo.cpp | 62 const TargetRegisterClass* RC = *I;
63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
64 (!BestRC || BestRC->hasSubClass(RC)))
65 BestRC = RC;
75 const TargetRegisterClass *RC, BitVector &R){
76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
82 const TargetRegisterClass *RC) const {
84 if (RC) {
85 getAllocatableSetForRC(MF, RC, Allocatable)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBank.cpp | 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
36 if (!covers(RC))
42 // RegisterBankInfo to find the subclasses of RC, to make sure
47 if (!RC.hasSubClassEq(&SubRC))
60 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
62 return ContainedRegClasses.test(RC.getID());
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
106 if (!covers(RC))
111 OS << TRI->getRegClassName(&RC);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| LiveStacks.cpp | 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
66 S2RCMap.insert(std::make_pair(Slot, RC));
70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
83 if (RC)
84 OS << " [" << TRI->getRegClassName(RC) << "]\n";
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| GCNRegPressure.cpp | 88 const auto RC = MRI.getRegClass(Reg);
90 return STI->isSGPRClass(RC) ?
91 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
92 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 58 const TargetRegisterClass &RC =
63 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
64 TRI.getSpillAlignment(RC), false);
73 const TargetRegisterClass &RC = Mips::GPR32RegClass;
78 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
97 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
101 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyReplacePhysRegs.cpp | 87 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
93 VReg = MRI.createVirtualRegister(RC);
|
| WebAssemblyInstrInfo.cpp | 59 const TargetRegisterClass *RC =
65 if (RC == &WebAssembly::I32RegClass)
67 else if (RC == &WebAssembly::I64RegClass)
69 else if (RC == &WebAssembly::F32RegClass)
71 else if (RC == &WebAssembly::F64RegClass)
|
| /external/u-boot/board/freescale/m5253demo/ |
| m5253demo.c | 33 u32 RC, temp;
35 RC = (CONFIG_SYS_CLK / 1000000) >> 1;
36 RC = (RC * 15) >> 4;
39 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
|
| /external/u-boot/board/freescale/m5253evbe/ |
| m5253evbe.c | 30 u32 RC, dramsize;
32 RC = (CONFIG_SYS_CLK / 1000000) >> 1;
33 RC = (RC * 15) >> 4;
36 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
|
| /external/u-boot/board/sysam/amcore/ |
| amcore.c | 55 u32 dramsize, RC;
76 * set proper RC as per specification
78 RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
79 RC = (RC * 15) >> 4;
82 out_be16(&dc->dcr, 0x8200 | RC);
|
| /external/llvm/lib/Target/X86/ |
| X86FixupSetCC.cpp | 160 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
163 unsigned ZeroReg = MRI->createVirtualRegister(RC);
164 unsigned InsertReg = MRI->createVirtualRegister(RC);
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 37 const CodeGenRegisterClass *RC;
257 const CodeGenRegisterClass *RC = nullptr;
261 RC = &Target.getRegisterClass(OpLeafRec);
263 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
265 RC = OrigDstRC;
270 if (!RC)
276 if (DstRC != RC && !DstRC->hasSubClass(RC))
279 DstRC = RC;
667 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86FixupSetCC.cpp | 161 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
164 unsigned ZeroReg = MRI->createVirtualRegister(RC);
165 unsigned InsertReg = MRI->createVirtualRegister(RC);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 37 const CodeGenRegisterClass *RC;
42 InstructionMemo(std::string Name, const CodeGenRegisterClass *RC,
45 : Name(Name), RC(RC), SubRegNo(SubRegNo), PhysRegs(PhysRegs),
264 const CodeGenRegisterClass *RC = nullptr;
268 RC = &Target.getRegisterClass(OpLeafRec);
270 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
272 RC = OrigDstRC;
277 if (!RC)
283 if (DstRC != RC && !DstRC->hasSubClass(RC)
[all...] |
| /external/apache-commons-bcel/src/main/java/org/apache/bcel/util/ |
| ClassLoaderRepository.java | 84 JavaClass RC = findClass(className);
85 if (RC != null) {
86 return RC;
93 RC = parser.parse();
94 storeClass(RC);
95 return RC;
|
