1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2015 4 * Texas Instruments Incorporated 5 * 6 * Lokesh Vutla <lokeshvutla (at) ti.com> 7 */ 8 9 #ifndef _DRA7_IODELAY_H_ 10 #define _DRA7_IODELAY_H_ 11 12 #include <common.h> 13 #include <asm/arch/sys_proto.h> 14 15 /* CONFIG_REG_0 */ 16 #define CFG_REG_0_OFFSET 0xC 17 #define CFG_REG_ROM_READ_SHIFT 1 18 #define CFG_REG_ROM_READ_MASK (1 << 1) 19 #define CFG_REG_CALIB_STRT_SHIFT 0 20 #define CFG_REG_CALIB_STRT_MASK (1 << 0) 21 #define CFG_REG_CALIB_STRT 1 22 #define CFG_REG_CALIB_END 0 23 #define CFG_REG_ROM_READ_START (1 << 1) 24 #define CFG_REG_ROM_READ_END (0 << 1) 25 26 /* CONFIG_REG_2 */ 27 #define CFG_REG_2_OFFSET 0x14 28 #define CFG_REG_REFCLK_PERIOD_SHIFT 0 29 #define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) 30 #define CFG_REG_REFCLK_PERIOD 0x2EF 31 32 /* CONFIG_REG_8 */ 33 #define CFG_REG_8_OFFSET 0x2C 34 #define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA 35 #define CFG_IODELAY_LOCK_KEY 0x0000AAAB 36 37 /* CONFIG_REG_3/4 */ 38 #define CFG_REG_3_OFFSET 0x18 39 #define CFG_REG_4_OFFSET 0x1C 40 #define CFG_REG_DLY_CNT_SHIFT 16 41 #define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) 42 #define CFG_REG_REF_CNT_SHIFT 0 43 #define CFG_REG_REF_CNT_MASK (0xFFFF << 0) 44 45 /* CTRL_CORE_SMA_SW_0 */ 46 #define CTRL_ISOLATE_SHIFT 2 47 #define CTRL_ISOLATE_MASK (1 << 2) 48 #define ISOLATE_IO 1 49 #define DEISOLATE_IO 0 50 51 /* CTRL_CORE_SMA_SW_1 */ 52 #define RGMII2_ID_MODE_N_MASK (1 << 26) 53 #define RGMII1_ID_MODE_N_MASK (1 << 25) 54 55 /* PRM_IO_PMCTRL */ 56 #define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 57 #define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) 58 #define PMCTRL_ISOCLK_STATUS_SHIFT 1 59 #define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) 60 #define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 61 #define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 62 63 #define ERR_CALIBRATE_IODELAY 0x1 64 #define ERR_DEISOLATE_IO 0x2 65 #define ERR_ISOLATE_IO 0x4 66 #define ERR_UPDATE_DELAY 0x8 67 #define ERR_CPDE 0x3 68 #define ERR_FPDE 0x5 69 70 /* CFG_XXX */ 71 #define CFG_X_SIGNATURE_SHIFT 12 72 #define CFG_X_SIGNATURE_MASK (0x3F << 12) 73 #define CFG_X_LOCK_SHIFT 10 74 #define CFG_X_LOCK_MASK (0x1 << 10) 75 #define CFG_X_COARSE_DLY_SHIFT 5 76 #define CFG_X_COARSE_DLY_MASK (0x1F << 5) 77 #define CFG_X_FINE_DLY_SHIFT 0 78 #define CFG_X_FINE_DLY_MASK (0x1F << 0) 79 #define CFG_X_SIGNATURE 0x29 80 #define CFG_X_LOCK 1 81 82 void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, 83 struct iodelay_cfg_entry const *iodelay, 84 int niodelays); 85 void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, 86 struct iodelay_cfg_entry const *iodelay, 87 int niodelays); 88 int __recalibrate_iodelay_start(void); 89 void __recalibrate_iodelay_end(int ret); 90 91 int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, 92 int niodelays); 93 #endif 94
