1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_S390_CONSTANTS_S390_H_ 6 #define V8_S390_CONSTANTS_S390_H_ 7 8 // Get the standard printf format macros for C99 stdint types. 9 #ifndef __STDC_FORMAT_MACROS 10 #define __STDC_FORMAT_MACROS 11 #endif 12 #include <inttypes.h> 13 14 #include <stdint.h> 15 16 #include "src/base/logging.h" 17 #include "src/base/macros.h" 18 #include "src/globals.h" 19 20 // UNIMPLEMENTED_ macro for S390. 21 #ifdef DEBUG 22 #define UNIMPLEMENTED_S390() \ 23 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ 24 __FILE__, __LINE__, __func__) 25 #else 26 #define UNIMPLEMENTED_S390() 27 #endif 28 29 namespace v8 { 30 namespace internal { 31 32 // TODO(sigurds): Change this value once we use relative jumps. 33 constexpr size_t kMaxPCRelativeCodeRangeInMB = 0; 34 35 // Number of registers 36 const int kNumRegisters = 16; 37 38 // FP support. 39 const int kNumDoubleRegisters = 16; 40 41 const int kNoRegister = -1; 42 43 // Actual value of root register is offset from the root array's start 44 // to take advantage of negative displacement values. 45 // TODO(sigurds): Choose best value. 46 constexpr int kRootRegisterBias = 128; 47 48 // sign-extend the least significant 16-bits of value <imm> 49 #define SIGN_EXT_IMM16(imm) ((static_cast<int>(imm) << 16) >> 16) 50 51 // sign-extend the least significant 26-bits of value <imm> 52 #define SIGN_EXT_IMM26(imm) ((static_cast<int>(imm) << 6) >> 6) 53 54 // ----------------------------------------------------------------------------- 55 // Conditions. 56 57 // Defines constants and accessor classes to assemble, disassemble and 58 // simulate z/Architecture instructions. 59 // 60 // Section references in the code refer to the "z/Architecture Principles 61 // Of Operation" http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr009.pdf 62 // 63 64 // Constants for specific fields are defined in their respective named enums. 65 // General constants are in an anonymous enum in class Instr. 66 enum Condition { 67 kNoCondition = -1, 68 eq = 0x8, // Equal. 69 ne = 0x7, // Not equal. 70 ge = 0xa, // Greater or equal. 71 lt = 0x4, // Less than. 72 gt = 0x2, // Greater than. 73 le = 0xc, // Less then or equal 74 al = 0xf, // Always. 75 76 CC_NOP = 0x0, // S390 NOP 77 CC_EQ = 0x08, // S390 condition code 0b1000 78 CC_LT = 0x04, // S390 condition code 0b0100 79 CC_LE = CC_EQ | CC_LT, // S390 condition code 0b1100 80 CC_GT = 0x02, // S390 condition code 0b0010 81 CC_GE = CC_EQ | CC_GT, // S390 condition code 0b1010 82 CC_OF = 0x01, // S390 condition code 0b0001 83 CC_NOF = 0x0E, // S390 condition code 0b1110 84 CC_ALWAYS = 0x0F, // S390 always taken branch 85 unordered = CC_OF, // Floating-point unordered 86 ordered = CC_NOF, // floating-point ordered 87 overflow = CC_OF, // Summary overflow 88 nooverflow = CC_NOF, 89 90 mask0x0 = 0, // no jumps 91 mask0x1 = 1, 92 mask0x2 = 2, 93 mask0x3 = 3, 94 mask0x4 = 4, 95 mask0x5 = 5, 96 mask0x6 = 6, 97 mask0x7 = 7, 98 mask0x8 = 8, 99 mask0x9 = 9, 100 mask0xA = 10, 101 mask0xB = 11, 102 mask0xC = 12, 103 mask0xD = 13, 104 mask0xE = 14, 105 mask0xF = 15, 106 107 // Rounding modes for floating poing facility 108 CURRENT_ROUNDING_MODE = 0, 109 ROUND_TO_NEAREST_WITH_TIES_AWAY_FROM_0 = 1, 110 ROUND_TO_PREPARE_FOR_SHORTER_PRECISION = 3, 111 ROUND_TO_NEAREST_WITH_TIES_TO_EVEN = 4, 112 ROUND_TOWARD_0 = 5, 113 ROUND_TOWARD_PLUS_INFINITE = 6, 114 ROUND_TOWARD_MINUS_INFINITE = 7 115 }; 116 117 inline Condition NegateCondition(Condition cond) { 118 DCHECK(cond != al); 119 switch (cond) { 120 case eq: 121 return ne; 122 case ne: 123 return eq; 124 case ge: 125 return lt; 126 case gt: 127 return le; 128 case le: 129 return gt; 130 case lt: 131 return ge; 132 case lt | gt: 133 return eq; 134 case le | ge: 135 return CC_OF; 136 case CC_OF: 137 return CC_NOF; 138 default: 139 DCHECK(false); 140 } 141 return al; 142 } 143 144 // ----------------------------------------------------------------------------- 145 // Instructions encoding. 146 147 // Instr is merely used by the Assembler to distinguish 32bit integers 148 // representing instructions from usual 32 bit values. 149 // Instruction objects are pointers to 32bit values, and provide methods to 150 // access the various ISA fields. 151 typedef int32_t Instr; 152 typedef uint16_t TwoByteInstr; 153 typedef uint32_t FourByteInstr; 154 typedef uint64_t SixByteInstr; 155 156 #define S390_RSY_A_OPCODE_LIST(V) \ 157 V(lmg, LMG, 0xEB04) /* type = RSY_A LOAD MULTIPLE (64) */ \ 158 V(srag, SRAG, 0xEB0A) /* type = RSY_A SHIFT RIGHT SINGLE (64) */ \ 159 V(slag, SLAG, 0xEB0B) /* type = RSY_A SHIFT LEFT SINGLE (64) */ \ 160 V(srlg, SRLG, 0xEB0C) /* type = RSY_A SHIFT RIGHT SINGLE LOGICAL (64) */ \ 161 V(sllg, SLLG, 0xEB0D) /* type = RSY_A SHIFT LEFT SINGLE LOGICAL (64) */ \ 162 V(tracg, TRACG, 0xEB0F) /* type = RSY_A TRACE (64) */ \ 163 V(csy, CSY, 0xEB14) /* type = RSY_A COMPARE AND SWAP (32) */ \ 164 V(rllg, RLLG, 0xEB1C) /* type = RSY_A ROTATE LEFT SINGLE LOGICAL (64) */ \ 165 V(rll, RLL, 0xEB1D) /* type = RSY_A ROTATE LEFT SINGLE LOGICAL (32) */ \ 166 V(stmg, STMG, 0xEB24) /* type = RSY_A STORE MULTIPLE (64) */ \ 167 V(stctg, STCTG, 0xEB25) /* type = RSY_A STORE CONTROL (64) */ \ 168 V(stmh, STMH, 0xEB26) /* type = RSY_A STORE MULTIPLE HIGH (32) */ \ 169 V(lctlg, LCTLG, 0xEB2F) /* type = RSY_A LOAD CONTROL (64) */ \ 170 V(csg, CSG, 0xEB30) /* type = RSY_A COMPARE AND SWAP (64) */ \ 171 V(cdsy, CDSY, 0xEB31) /* type = RSY_A COMPARE DOUBLE AND SWAP (32) */ \ 172 V(cdsg, CDSG, 0xEB3E) /* type = RSY_A COMPARE DOUBLE AND SWAP (64) */ \ 173 V(bxhg, BXHG, 0xEB44) /* type = RSY_A BRANCH ON INDEX HIGH (64) */ \ 174 V(bxleg, BXLEG, 0xEB45) /* type = RSY_A BRANCH ON INDEX LOW OR EQUAL (64) */ \ 175 V(ecag, ECAG, 0xEB4C) /* type = RSY_A EXTRACT CPU ATTRIBUTE */ \ 176 V(mvclu, MVCLU, 0xEB8E) /* type = RSY_A MOVE LONG UNICODE */ \ 177 V(clclu, CLCLU, 0xEB8F) /* type = RSY_A COMPARE LOGICAL LONG UNICODE */ \ 178 V(stmy, STMY, 0xEB90) /* type = RSY_A STORE MULTIPLE (32) */ \ 179 V(lmh, LMH, 0xEB96) /* type = RSY_A LOAD MULTIPLE HIGH (32) */ \ 180 V(lmy, LMY, 0xEB98) /* type = RSY_A LOAD MULTIPLE (32) */ \ 181 V(lamy, LAMY, 0xEB9A) /* type = RSY_A LOAD ACCESS MULTIPLE */ \ 182 V(stamy, STAMY, 0xEB9B) /* type = RSY_A STORE ACCESS MULTIPLE */ \ 183 V(srak, SRAK, 0xEBDC) /* type = RSY_A SHIFT RIGHT SINGLE (32) */ \ 184 V(slak, SLAK, 0xEBDD) /* type = RSY_A SHIFT LEFT SINGLE (32) */ \ 185 V(srlk, SRLK, 0xEBDE) /* type = RSY_A SHIFT RIGHT SINGLE LOGICAL (32) */ \ 186 V(sllk, SLLK, 0xEBDF) /* type = RSY_A SHIFT LEFT SINGLE LOGICAL (32) */ \ 187 V(lang, LANG, 0xEBE4) /* type = RSY_A LOAD AND AND (64) */ \ 188 V(laog, LAOG, 0xEBE6) /* type = RSY_A LOAD AND OR (64) */ \ 189 V(laxg, LAXG, 0xEBE7) /* type = RSY_A LOAD AND EXCLUSIVE OR (64) */ \ 190 V(laag, LAAG, 0xEBE8) /* type = RSY_A LOAD AND ADD (64) */ \ 191 V(laalg, LAALG, 0xEBEA) /* type = RSY_A LOAD AND ADD LOGICAL (64) */ \ 192 V(lan, LAN, 0xEBF4) /* type = RSY_A LOAD AND AND (32) */ \ 193 V(lao, LAO, 0xEBF6) /* type = RSY_A LOAD AND OR (32) */ \ 194 V(lax, LAX, 0xEBF7) /* type = RSY_A LOAD AND EXCLUSIVE OR (32) */ \ 195 V(laa, LAA, 0xEBF8) /* type = RSY_A LOAD AND ADD (32) */ \ 196 V(laal, LAAL, 0xEBFA) /* type = RSY_A LOAD AND ADD LOGICAL (32) */ 197 198 #define S390_RSY_B_OPCODE_LIST(V) \ 199 V(clmh, CLMH, \ 200 0xEB20) /* type = RSY_B COMPARE LOGICAL CHAR. UNDER MASK (high) */ \ 201 V(clmy, CLMY, \ 202 0xEB21) /* type = RSY_B COMPARE LOGICAL CHAR. UNDER MASK (low) */ \ 203 V(clt, CLT, 0xEB23) /* type = RSY_B COMPARE LOGICAL AND TRAP (32) */ \ 204 V(clgt, CLGT, 0xEB2B) /* type = RSY_B COMPARE LOGICAL AND TRAP (64) */ \ 205 V(stcmh, STCMH, \ 206 0xEB2C) /* type = RSY_B STORE CHARACTERS UNDER MASK (high) */ \ 207 V(stcmy, STCMY, 0xEB2D) /* type = RSY_B STORE CHARACTERS UNDER MASK (low) */ \ 208 V(icmh, ICMH, 0xEB80) /* type = RSY_B INSERT CHARACTERS UNDER MASK (high) */ \ 209 V(icmy, ICMY, 0xEB81) /* type = RSY_B INSERT CHARACTERS UNDER MASK (low) */ \ 210 V(locfh, LOCFH, 0xEBE0) /* type = RSY_B LOAD HIGH ON CONDITION (32) */ \ 211 V(stocfh, STOCFH, 0xEBE1) /* type = RSY_B STORE HIGH ON CONDITION */ \ 212 V(locg, LOCG, 0xEBE2) /* type = RSY_B LOAD ON CONDITION (64) */ \ 213 V(stocg, STOCG, 0xEBE3) /* type = RSY_B STORE ON CONDITION (64) */ \ 214 V(loc, LOC, 0xEBF2) /* type = RSY_B LOAD ON CONDITION (32) */ \ 215 V(stoc, STOC, 0xEBF3) /* type = RSY_B STORE ON CONDITION (32) */ 216 217 #define S390_RXE_OPCODE_LIST(V) \ 218 V(lcbb, LCBB, 0xE727) /* type = RXE LOAD COUNT TO BLOCK BOUNDARY */ \ 219 V(ldeb, LDEB, 0xED04) /* type = RXE LOAD LENGTHENED (short to long BFP) */ \ 220 V(lxdb, LXDB, \ 221 0xED05) /* type = RXE LOAD LENGTHENED (long to extended BFP) */ \ 222 V(lxeb, LXEB, \ 223 0xED06) /* type = RXE LOAD LENGTHENED (short to extended BFP) */ \ 224 V(mxdb, MXDB, 0xED07) /* type = RXE MULTIPLY (long to extended BFP) */ \ 225 V(keb, KEB, 0xED08) /* type = RXE COMPARE AND SIGNAL (short BFP) */ \ 226 V(ceb, CEB, 0xED09) /* type = RXE COMPARE (short BFP) */ \ 227 V(aeb, AEB, 0xED0A) /* type = RXE ADD (short BFP) */ \ 228 V(seb, SEB, 0xED0B) /* type = RXE SUBTRACT (short BFP) */ \ 229 V(mdeb, MDEB, 0xED0C) /* type = RXE MULTIPLY (short to long BFP) */ \ 230 V(deb, DEB, 0xED0D) /* type = RXE DIVIDE (short BFP) */ \ 231 V(tceb, TCEB, 0xED10) /* type = RXE TEST DATA CLASS (short BFP) */ \ 232 V(tcdb, TCDB, 0xED11) /* type = RXE TEST DATA CLASS (long BFP) */ \ 233 V(tcxb, TCXB, 0xED12) /* type = RXE TEST DATA CLASS (extended BFP) */ \ 234 V(sqeb, SQEB, 0xED14) /* type = RXE SQUARE ROOT (short BFP) */ \ 235 V(sqdb, SQDB, 0xED15) /* type = RXE SQUARE ROOT (long BFP) */ \ 236 V(meeb, MEEB, 0xED17) /* type = RXE MULTIPLY (short BFP) */ \ 237 V(kdb, KDB, 0xED18) /* type = RXE COMPARE AND SIGNAL (long BFP) */ \ 238 V(cdb, CDB, 0xED19) /* type = RXE COMPARE (long BFP) */ \ 239 V(adb, ADB, 0xED1A) /* type = RXE ADD (long BFP) */ \ 240 V(sdb, SDB, 0xED1B) /* type = RXE SUBTRACT (long BFP) */ \ 241 V(mdb, MDB, 0xED1C) /* type = RXE MULTIPLY (long BFP) */ \ 242 V(ddb, DDB, 0xED1D) /* type = RXE DIVIDE (long BFP) */ \ 243 V(lde, LDE, 0xED24) /* type = RXE LOAD LENGTHENED (short to long HFP) */ \ 244 V(lxd, LXD, \ 245 0xED25) /* type = RXE LOAD LENGTHENED (long to extended HFP) */ \ 246 V(lxe, LXE, \ 247 0xED26) /* type = RXE LOAD LENGTHENED (short to extended HFP) */ \ 248 V(sqe, SQE, 0xED34) /* type = RXE SQUARE ROOT (short HFP) */ \ 249 V(sqd, SQD, 0xED35) /* type = RXE SQUARE ROOT (long HFP) */ \ 250 V(mee, MEE, 0xED37) /* type = RXE MULTIPLY (short HFP) */ \ 251 V(tdcet, TDCET, 0xED50) /* type = RXE TEST DATA CLASS (short DFP) */ \ 252 V(tdget, TDGET, 0xED51) /* type = RXE TEST DATA GROUP (short DFP) */ \ 253 V(tdcdt, TDCDT, 0xED54) /* type = RXE TEST DATA CLASS (long DFP) */ \ 254 V(tdgdt, TDGDT, 0xED55) /* type = RXE TEST DATA GROUP (long DFP) */ \ 255 V(tdcxt, TDCXT, 0xED58) /* type = RXE TEST DATA CLASS (extended DFP) */ \ 256 V(tdgxt, TDGXT, 0xED59) /* type = RXE TEST DATA GROUP (extended DFP) */ 257 258 #define S390_RRF_A_OPCODE_LIST(V) \ 259 V(ipte, IPTE, 0xB221) /* type = RRF_A INVALIDATE PAGE TABLE ENTRY */ \ 260 V(mdtra, MDTRA, 0xB3D0) /* type = RRF_A MULTIPLY (long DFP) */ \ 261 V(ddtra, DDTRA, 0xB3D1) /* type = RRF_A DIVIDE (long DFP) */ \ 262 V(adtra, ADTRA, 0xB3D2) /* type = RRF_A ADD (long DFP) */ \ 263 V(sdtra, SDTRA, 0xB3D3) /* type = RRF_A SUBTRACT (long DFP) */ \ 264 V(mxtra, MXTRA, 0xB3D8) /* type = RRF_A MULTIPLY (extended DFP) */ \ 265 V(msrkc, MSRKC, 0xB9FD) /* type = RRF_A MULTIPLY (32)*/ \ 266 V(msgrkc, MSGRKC, 0xB9ED) /* type = RRF_A MULTIPLY (64)*/ \ 267 V(dxtra, DXTRA, 0xB3D9) /* type = RRF_A DIVIDE (extended DFP) */ \ 268 V(axtra, AXTRA, 0xB3DA) /* type = RRF_A ADD (extended DFP) */ \ 269 V(sxtra, SXTRA, 0xB3DB) /* type = RRF_A SUBTRACT (extended DFP) */ \ 270 V(ahhhr, AHHHR, 0xB9C8) /* type = RRF_A ADD HIGH (32) */ \ 271 V(shhhr, SHHHR, 0xB9C9) /* type = RRF_A SUBTRACT HIGH (32) */ \ 272 V(alhhhr, ALHHHR, 0xB9CA) /* type = RRF_A ADD LOGICAL HIGH (32) */ \ 273 V(slhhhr, SLHHHR, 0xB9CB) /* type = RRF_A SUBTRACT LOGICAL HIGH (32) */ \ 274 V(ahhlr, AHHLR, 0xB9D8) /* type = RRF_A ADD HIGH (32) */ \ 275 V(shhlr, SHHLR, 0xB9D9) /* type = RRF_A SUBTRACT HIGH (32) */ \ 276 V(alhhlr, ALHHLR, 0xB9DA) /* type = RRF_A ADD LOGICAL HIGH (32) */ \ 277 V(slhhlr, SLHHLR, 0xB9DB) /* type = RRF_A SUBTRACT LOGICAL HIGH (32) */ \ 278 V(ngrk, NGRK, 0xB9E4) /* type = RRF_A AND (64) */ \ 279 V(ogrk, OGRK, 0xB9E6) /* type = RRF_A OR (64) */ \ 280 V(xgrk, XGRK, 0xB9E7) /* type = RRF_A EXCLUSIVE OR (64) */ \ 281 V(agrk, AGRK, 0xB9E8) /* type = RRF_A ADD (64) */ \ 282 V(sgrk, SGRK, 0xB9E9) /* type = RRF_A SUBTRACT (64) */ \ 283 V(algrk, ALGRK, 0xB9EA) /* type = RRF_A ADD LOGICAL (64) */ \ 284 V(slgrk, SLGRK, 0xB9EB) /* type = RRF_A SUBTRACT LOGICAL (64) */ \ 285 V(nrk, NRK, 0xB9F4) /* type = RRF_A AND (32) */ \ 286 V(ork, ORK, 0xB9F6) /* type = RRF_A OR (32) */ \ 287 V(xrk, XRK, 0xB9F7) /* type = RRF_A EXCLUSIVE OR (32) */ \ 288 V(ark, ARK, 0xB9F8) /* type = RRF_A ADD (32) */ \ 289 V(srk, SRK, 0xB9F9) /* type = RRF_A SUBTRACT (32) */ \ 290 V(alrk, ALRK, 0xB9FA) /* type = RRF_A ADD LOGICAL (32) */ \ 291 V(slrk, SLRK, 0xB9FB) /* type = RRF_A SUBTRACT LOGICAL (32) */ 292 293 #define S390_RXF_OPCODE_LIST(V) \ 294 V(maeb, MAEB, 0xED0E) /* type = RXF MULTIPLY AND ADD (short BFP) */ \ 295 V(mseb, MSEB, 0xED0F) /* type = RXF MULTIPLY AND SUBTRACT (short BFP) */ \ 296 V(madb, MADB, 0xED1E) /* type = RXF MULTIPLY AND ADD (long BFP) */ \ 297 V(msdb, MSDB, 0xED1F) /* type = RXF MULTIPLY AND SUBTRACT (long BFP) */ \ 298 V(mae, MAE, 0xED2E) /* type = RXF MULTIPLY AND ADD (short HFP) */ \ 299 V(mse, MSE, 0xED2F) /* type = RXF MULTIPLY AND SUBTRACT (short HFP) */ \ 300 V(mayl, MAYL, \ 301 0xED38) /* type = RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) */ \ 302 V(myl, MYL, \ 303 0xED39) /* type = RXF MULTIPLY UNNORM. (long to ext. low HFP) */ \ 304 V(may, MAY, \ 305 0xED3A) /* type = RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) */ \ 306 V(my, MY, \ 307 0xED3B) /* type = RXF MULTIPLY UNNORMALIZED (long to ext. HFP) */ \ 308 V(mayh, MAYH, \ 309 0xED3C) /* type = RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) */ \ 310 V(myh, MYH, \ 311 0xED3D) /* type = RXF MULTIPLY UNNORM. (long to ext. high HFP) */ \ 312 V(mad, MAD, 0xED3E) /* type = RXF MULTIPLY AND ADD (long HFP) */ \ 313 V(msd, MSD, 0xED3F) /* type = RXF MULTIPLY AND SUBTRACT (long HFP) */ \ 314 V(sldt, SLDT, 0xED40) /* type = RXF SHIFT SIGNIFICAND LEFT (long DFP) */ \ 315 V(srdt, SRDT, 0xED41) /* type = RXF SHIFT SIGNIFICAND RIGHT (long DFP) */ \ 316 V(slxt, SLXT, \ 317 0xED48) /* type = RXF SHIFT SIGNIFICAND LEFT (extended DFP) */ \ 318 V(srxt, SRXT, \ 319 0xED49) /* type = RXF SHIFT SIGNIFICAND RIGHT (extended DFP) */ 320 321 #define S390_IE_OPCODE_LIST(V) \ 322 V(niai, NIAI, 0xB2FA) /* type = IE NEXT INSTRUCTION ACCESS INTENT */ 323 324 #define S390_RRF_B_OPCODE_LIST(V) \ 325 V(diebr, DIEBR, 0xB353) /* type = RRF_B DIVIDE TO INTEGER (short BFP) */ \ 326 V(didbr, DIDBR, 0xB35B) /* type = RRF_B DIVIDE TO INTEGER (long BFP) */ \ 327 V(cpsdr, CPSDR, 0xB372) /* type = RRF_B COPY SIGN (long) */ \ 328 V(qadtr, QADTR, 0xB3F5) /* type = RRF_B QUANTIZE (long DFP) */ \ 329 V(iedtr, IEDTR, \ 330 0xB3F6) /* type = RRF_B INSERT BIASED EXPONENT (64 to long DFP) */ \ 331 V(rrdtr, RRDTR, 0xB3F7) /* type = RRF_B REROUND (long DFP) */ \ 332 V(qaxtr, QAXTR, 0xB3FD) /* type = RRF_B QUANTIZE (extended DFP) */ \ 333 V(iextr, IEXTR, \ 334 0xB3FE) /* type = RRF_B INSERT BIASED EXPONENT (64 to extended DFP) */ \ 335 V(rrxtr, RRXTR, 0xB3FF) /* type = RRF_B REROUND (extended DFP) */ \ 336 V(kmctr, KMCTR, 0xB92D) /* type = RRF_B CIPHER MESSAGE WITH COUNTER */ \ 337 V(idte, IDTE, 0xB98E) /* type = RRF_B INVALIDATE DAT TABLE ENTRY */ \ 338 V(crdte, CRDTE, \ 339 0xB98F) /* type = RRF_B COMPARE AND REPLACE DAT TABLE ENTRY */ \ 340 V(lptea, LPTEA, 0xB9AA) /* type = RRF_B LOAD PAGE TABLE ENTRY ADDRESS */ 341 342 #define S390_RRF_C_OPCODE_LIST(V) \ 343 V(sske, SSKE, 0xB22B) /* type = RRF_C SET STORAGE KEY EXTENDED */ \ 344 V(cu21, CU21, 0xB2A6) /* type = RRF_C CONVERT UTF-16 TO UTF-8 */ \ 345 V(cu12, CU12, 0xB2A7) /* type = RRF_C CONVERT UTF-8 TO UTF-16 */ \ 346 V(ppa, PPA, 0xB2E8) /* type = RRF_C PERFORM PROCESSOR ASSIST */ \ 347 V(cgrt, CGRT, 0xB960) /* type = RRF_C COMPARE AND TRAP (64) */ \ 348 V(clgrt, CLGRT, 0xB961) /* type = RRF_C COMPARE LOGICAL AND TRAP (64) */ \ 349 V(crt, CRT, 0xB972) /* type = RRF_C COMPARE AND TRAP (32) */ \ 350 V(clrt, CLRT, 0xB973) /* type = RRF_C COMPARE LOGICAL AND TRAP (32) */ \ 351 V(trtt, TRTT, 0xB990) /* type = RRF_C TRANSLATE TWO TO TWO */ \ 352 V(trto, TRTO, 0xB991) /* type = RRF_C TRANSLATE TWO TO ONE */ \ 353 V(trot, TROT, 0xB992) /* type = RRF_C TRANSLATE ONE TO TWO */ \ 354 V(troo, TROO, 0xB993) /* type = RRF_C TRANSLATE ONE TO ONE */ \ 355 V(cu14, CU14, 0xB9B0) /* type = RRF_C CONVERT UTF-8 TO UTF-32 */ \ 356 V(cu24, CU24, 0xB9B1) /* type = RRF_C CONVERT UTF-16 TO UTF-32 */ \ 357 V(trtre, TRTRE, \ 358 0xB9BD) /* type = RRF_C TRANSLATE AND TEST REVERSE EXTENDED */ \ 359 V(trte, TRTE, 0xB9BF) /* type = RRF_C TRANSLATE AND TEST EXTENDED */ \ 360 V(locfhr, LOCFHR, 0xB9E0) /* type = RRF_C LOAD HIGH ON CONDITION (32) */ \ 361 V(locgr, LOCGR, 0xB9E2) /* type = RRF_C LOAD ON CONDITION (64) */ \ 362 V(locr, LOCR, 0xB9F2) /* type = RRF_C LOAD ON CONDITION (32) */ 363 364 #define S390_MII_OPCODE_LIST(V) \ 365 V(bprp, BPRP, 0xC5) /* type = MII BRANCH PREDICTION RELATIVE PRELOAD */ 366 367 #define S390_RRF_D_OPCODE_LIST(V) \ 368 V(ldetr, LDETR, \ 369 0xB3D4) /* type = RRF_D LOAD LENGTHENED (short to long DFP) */ \ 370 V(lxdtr, LXDTR, \ 371 0xB3DC) /* type = RRF_D LOAD LENGTHENED (long to extended DFP) */ \ 372 V(csdtr, CSDTR, \ 373 0xB3E3) /* type = RRF_D CONVERT TO SIGNED PACKED (long DFP to 64) */ \ 374 V(csxtr, CSXTR, \ 375 0xB3EB) /* type = RRF_D CONVERT TO SIGNED PACKED (extended DFP to 128) */ 376 377 #define S390_RRF_E_OPCODE_LIST(V) \ 378 V(ledbra, LEDBRA, \ 379 0xB344) /* type = RRF_E LOAD ROUNDED (long to short BFP) */ \ 380 V(ldxbra, LDXBRA, \ 381 0xB345) /* type = RRF_E LOAD ROUNDED (extended to long BFP) */ \ 382 V(lexbra, LEXBRA, \ 383 0xB346) /* type = RRF_E LOAD ROUNDED (extended to short BFP) */ \ 384 V(fixbra, FIXBRA, 0xB347) /* type = RRF_E LOAD FP INTEGER (extended BFP) */ \ 385 V(tbedr, TBEDR, \ 386 0xB350) /* type = RRF_E CONVERT HFP TO BFP (long to short) */ \ 387 V(tbdr, TBDR, 0xB351) /* type = RRF_E CONVERT HFP TO BFP (long) */ \ 388 V(fiebra, FIEBRA, 0xB357) /* type = RRF_E LOAD FP INTEGER (short BFP) */ \ 389 V(fidbra, FIDBRA, 0xB35F) /* type = RRF_E LOAD FP INTEGER (long BFP) */ \ 390 V(celfbr, CELFBR, \ 391 0xB390) /* type = RRF_E CONVERT FROM LOGICAL (32 to short BFP) */ \ 392 V(cdlfbr, CDLFBR, \ 393 0xB391) /* type = RRF_E CONVERT FROM LOGICAL (32 to long BFP) */ \ 394 V(cxlfbr, CXLFBR, \ 395 0xB392) /* type = RRF_E CONVERT FROM LOGICAL (32 to extended BFP) */ \ 396 V(cefbra, CEFBRA, \ 397 0xB394) /* type = RRF_E CONVERT FROM FIXED (32 to short BFP) */ \ 398 V(cdfbra, CDFBRA, \ 399 0xB395) /* type = RRF_E CONVERT FROM FIXED (32 to long BFP) */ \ 400 V(cxfbra, CXFBRA, \ 401 0xB396) /* type = RRF_E CONVERT FROM FIXED (32 to extended BFP) */ \ 402 V(cfebra, CFEBRA, \ 403 0xB398) /* type = RRF_E CONVERT TO FIXED (short BFP to 32) */ \ 404 V(cfdbra, CFDBRA, \ 405 0xB399) /* type = RRF_E CONVERT TO FIXED (long BFP to 32) */ \ 406 V(cfxbra, CFXBRA, \ 407 0xB39A) /* type = RRF_E CONVERT TO FIXED (extended BFP to 32) */ \ 408 V(clfebr, CLFEBR, \ 409 0xB39C) /* type = RRF_E CONVERT TO LOGICAL (short BFP to 32) */ \ 410 V(clfdbr, CLFDBR, \ 411 0xB39D) /* type = RRF_E CONVERT TO LOGICAL (long BFP to 32) */ \ 412 V(clfxbr, CLFXBR, \ 413 0xB39E) /* type = RRF_E CONVERT TO LOGICAL (extended BFP to 32) */ \ 414 V(celgbr, CELGBR, \ 415 0xB3A0) /* type = RRF_E CONVERT FROM LOGICAL (64 to short BFP) */ \ 416 V(cdlgbr, CDLGBR, \ 417 0xB3A1) /* type = RRF_E CONVERT FROM LOGICAL (64 to long BFP) */ \ 418 V(cxlgbr, CXLGBR, \ 419 0xB3A2) /* type = RRF_E CONVERT FROM LOGICAL (64 to extended BFP) */ \ 420 V(cegbra, CEGBRA, \ 421 0xB3A4) /* type = RRF_E CONVERT FROM FIXED (64 to short BFP) */ \ 422 V(cdgbra, CDGBRA, \ 423 0xB3A5) /* type = RRF_E CONVERT FROM FIXED (64 to long BFP) */ \ 424 V(cxgbra, CXGBRA, \ 425 0xB3A6) /* type = RRF_E CONVERT FROM FIXED (64 to extended BFP) */ \ 426 V(cgebra, CGEBRA, \ 427 0xB3A8) /* type = RRF_E CONVERT TO FIXED (short BFP to 64) */ \ 428 V(cgdbra, CGDBRA, \ 429 0xB3A9) /* type = RRF_E CONVERT TO FIXED (long BFP to 64) */ \ 430 V(cgxbra, CGXBRA, \ 431 0xB3AA) /* type = RRF_E CONVERT TO FIXED (extended BFP to 64) */ \ 432 V(clgebr, CLGEBR, \ 433 0xB3AC) /* type = RRF_E CONVERT TO LOGICAL (short BFP to 64) */ \ 434 V(clgdbr, CLGDBR, \ 435 0xB3AD) /* type = RRF_E CONVERT TO LOGICAL (long BFP to 64) */ \ 436 V(clgxbr, CLGXBR, \ 437 0xB3AE) /* type = RRF_E CONVERT TO LOGICAL (extended BFP to 64) */ \ 438 V(cfer, CFER, 0xB3B8) /* type = RRF_E CONVERT TO FIXED (short HFP to 32) */ \ 439 V(cfdr, CFDR, 0xB3B9) /* type = RRF_E CONVERT TO FIXED (long HFP to 32) */ \ 440 V(cfxr, CFXR, \ 441 0xB3BA) /* type = RRF_E CONVERT TO FIXED (extended HFP to 32) */ \ 442 V(cger, CGER, 0xB3C8) /* type = RRF_E CONVERT TO FIXED (short HFP to 64) */ \ 443 V(cgdr, CGDR, 0xB3C9) /* type = RRF_E CONVERT TO FIXED (long HFP to 64) */ \ 444 V(cgxr, CGXR, \ 445 0xB3CA) /* type = RRF_E CONVERT TO FIXED (extended HFP to 64) */ \ 446 V(ledtr, LEDTR, 0xB3D5) /* type = RRF_E LOAD ROUNDED (long to short DFP) */ \ 447 V(fidtr, FIDTR, 0xB3D7) /* type = RRF_E LOAD FP INTEGER (long DFP) */ \ 448 V(ldxtr, LDXTR, \ 449 0xB3DD) /* type = RRF_E LOAD ROUNDED (extended to long DFP) */ \ 450 V(fixtr, FIXTR, 0xB3DF) /* type = RRF_E LOAD FP INTEGER (extended DFP) */ \ 451 V(cgdtra, CGDTRA, \ 452 0xB3E1) /* type = RRF_E CONVERT TO FIXED (long DFP to 64) */ \ 453 V(cgxtra, CGXTRA, \ 454 0xB3E9) /* type = RRF_E CONVERT TO FIXED (extended DFP to 64) */ \ 455 V(cdgtra, CDGTRA, \ 456 0xB3F1) /* type = RRF_E CONVERT FROM FIXED (64 to long DFP) */ \ 457 V(cxgtra, CXGTRA, \ 458 0xB3F9) /* type = RRF_E CONVERT FROM FIXED (64 to extended DFP) */ \ 459 V(cfdtr, CFDTR, 0xB941) /* type = RRF_E CONVERT TO FIXED (long DFP to 32) */ \ 460 V(clgdtr, CLGDTR, \ 461 0xB942) /* type = RRF_E CONVERT TO LOGICAL (long DFP to 64) */ \ 462 V(clfdtr, CLFDTR, \ 463 0xB943) /* type = RRF_E CONVERT TO LOGICAL (long DFP to 32) */ \ 464 V(cfxtr, CFXTR, \ 465 0xB949) /* type = RRF_E CONVERT TO FIXED (extended DFP to 32) */ \ 466 V(clgxtr, CLGXTR, \ 467 0xB94A) /* type = RRF_E CONVERT TO LOGICAL (extended DFP to 64) */ \ 468 V(clfxtr, CLFXTR, \ 469 0xB94B) /* type = RRF_E CONVERT TO LOGICAL (extended DFP to 32) */ \ 470 V(cdlgtr, CDLGTR, \ 471 0xB952) /* type = RRF_E CONVERT FROM LOGICAL (64 to long DFP) */ \ 472 V(cdlftr, CDLFTR, \ 473 0xB953) /* type = RRF_E CONVERT FROM LOGICAL (32 to long DFP) */ \ 474 V(cxlgtr, CXLGTR, \ 475 0xB95A) /* type = RRF_E CONVERT FROM LOGICAL (64 to extended DFP) */ \ 476 V(cxlftr, CXLFTR, \ 477 0xB95B) /* type = RRF_E CONVERT FROM LOGICAL (32 to extended DFP) */ 478 479 #define S390_VRR_A_OPCODE_LIST(V) \ 480 V(vpopct, VPOPCT, 0xE750) /* type = VRR_A VECTOR POPULATION COUNT */ \ 481 V(vctz, VCTZ, 0xE752) /* type = VRR_A VECTOR COUNT TRAILING ZEROS */ \ 482 V(vclz, VCLZ, 0xE753) /* type = VRR_A VECTOR COUNT LEADING ZEROS */ \ 483 V(vlr, VLR, 0xE756) /* type = VRR_A VECTOR LOAD */ \ 484 V(vistr, VISTR, 0xE75C) /* type = VRR_A VECTOR ISOLATE STRING */ \ 485 V(vseg, VSEG, 0xE75F) /* type = VRR_A VECTOR SIGN EXTEND TO DOUBLEWORD */ \ 486 V(vclgd, VCLGD, \ 487 0xE7C0) /* type = VRR_A VECTOR FP CONVERT TO LOGICAL 64-BIT */ \ 488 V(vcdlg, VCDLG, \ 489 0xE7C1) /* type = VRR_A VECTOR FP CONVERT FROM LOGICAL 64-BIT */ \ 490 V(vcgd, VCGD, 0xE7C2) /* type = VRR_A VECTOR FP CONVERT TO FIXED 64-BIT */ \ 491 V(vcdg, VCDG, 0xE7C3) /* type = VRR_A VECTOR FP CONVERT FROM FIXED 64-BIT */ \ 492 V(vlde, VLDE, 0xE7C4) /* type = VRR_A VECTOR FP LOAD LENGTHENED */ \ 493 V(vled, VLED, 0xE7C5) /* type = VRR_A VECTOR FP LOAD ROUNDED */ \ 494 V(vfi, VFI, 0xE7C7) /* type = VRR_A VECTOR LOAD FP INTEGER */ \ 495 V(wfk, WFK, 0xE7CA) /* type = VRR_A VECTOR FP COMPARE AND SIGNAL SCALAR */ \ 496 V(wfc, WFC, 0xE7CB) /* type = VRR_A VECTOR FP COMPARE SCALAR */ \ 497 V(vfpso, VFPSO, 0xE7CC) /* type = VRR_A VECTOR FP PERFORM SIGN OPERATION */ \ 498 V(vfsq, VFSQ, 0xE7CE) /* type = VRR_A VECTOR FP SQUARE ROOT */ \ 499 V(vupll, VUPLL, 0xE7D4) /* type = VRR_A VECTOR UNPACK LOGICAL LOW */ \ 500 V(vuplh, VUPLH, 0xE7D5) /* type = VRR_A VECTOR UNPACK LOGICAL HIGH */ \ 501 V(vupl, VUPL, 0xE7D6) /* type = VRR_A VECTOR UNPACK LOW */ \ 502 V(vuph, VUPH, 0xE7D7) /* type = VRR_A VECTOR UNPACK HIGH */ \ 503 V(vtm, VTM, 0xE7D8) /* type = VRR_A VECTOR TEST UNDER MASK */ \ 504 V(vecl, VECL, 0xE7D9) /* type = VRR_A VECTOR ELEMENT COMPARE LOGICAL */ \ 505 V(vec, VEC, 0xE7DB) /* type = VRR_A VECTOR ELEMENT COMPARE */ \ 506 V(vlc, VLC, 0xE7DE) /* type = VRR_A VECTOR LOAD COMPLEMENT */ \ 507 V(vlp, VLP, 0xE7DF) /* type = VRR_A VECTOR LOAD POSITIVE */ 508 509 #define S390_VRR_B_OPCODE_LIST(V) \ 510 V(vfee, VFEE, 0xE780) /* type = VRR_B VECTOR FIND ELEMENT EQUAL */ \ 511 V(vfene, VFENE, 0xE781) /* type = VRR_B VECTOR FIND ELEMENT NOT EQUAL */ \ 512 V(vfae, VFAE, 0xE782) /* type = VRR_B VECTOR FIND ANY ELEMENT EQUAL */ \ 513 V(vpkls, VPKLS, 0xE795) /* type = VRR_B VECTOR PACK LOGICAL SATURATE */ \ 514 V(vpks, VPKS, 0xE797) /* type = VRR_B VECTOR PACK SATURATE */ \ 515 V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \ 516 V(vchl, VCHL, 0xE7F9) /* type = VRR_B VECTOR COMPARE HIGH LOGICAL */ \ 517 V(vch, VCH, 0xE7FB) /* type = VRR_B VECTOR COMPARE HIGH */ 518 519 #define S390_VRR_C_OPCODE_LIST(V) \ 520 V(vmrl, VMRL, 0xE760) /* type = VRR_C VECTOR MERGE LOW */ \ 521 V(vmrh, VMRH, 0xE761) /* type = VRR_C VECTOR MERGE HIGH */ \ 522 V(vsum, VSUM, 0xE764) /* type = VRR_C VECTOR SUM ACROSS WORD */ \ 523 V(vsumg, VSUMG, 0xE765) /* type = VRR_C VECTOR SUM ACROSS DOUBLEWORD */ \ 524 V(vcksm, VCKSM, 0xE766) /* type = VRR_C VECTOR CHECKSUM */ \ 525 V(vsumq, VSUMQ, 0xE767) /* type = VRR_C VECTOR SUM ACROSS QUADWORD */ \ 526 V(vn, VN, 0xE768) /* type = VRR_C VECTOR AND */ \ 527 V(vnc, VNC, 0xE769) /* type = VRR_C VECTOR AND WITH COMPLEMENT */ \ 528 V(vo, VO, 0xE76A) /* type = VRR_C VECTOR OR */ \ 529 V(vno, VNO, 0xE76B) /* type = VRR_C VECTOR NOR */ \ 530 V(vx, VX, 0xE76D) /* type = VRR_C VECTOR EXCLUSIVE OR */ \ 531 V(veslv, VESLV, 0xE770) /* type = VRR_C VECTOR ELEMENT SHIFT LEFT */ \ 532 V(verllv, VERLLV, \ 533 0xE773) /* type = VRR_C VECTOR ELEMENT ROTATE LEFT LOGICAL */ \ 534 V(vsl, VSL, 0xE774) /* type = VRR_C VECTOR SHIFT LEFT */ \ 535 V(vslb, VSLB, 0xE775) /* type = VRR_C VECTOR SHIFT LEFT BY BYTE */ \ 536 V(vesrlv, VESRLV, \ 537 0xE778) /* type = VRR_C VECTOR ELEMENT SHIFT RIGHT LOGICAL */ \ 538 V(vesrav, VESRAV, \ 539 0xE77A) /* type = VRR_C VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ \ 540 V(vsrl, VSRL, 0xE77C) /* type = VRR_C VECTOR SHIFT RIGHT LOGICAL */ \ 541 V(vsrlb, VSRLB, \ 542 0xE77D) /* type = VRR_C VECTOR SHIFT RIGHT LOGICAL BY BYTE */ \ 543 V(vsra, VSRA, 0xE77E) /* type = VRR_C VECTOR SHIFT RIGHT ARITHMETIC */ \ 544 V(vsrab, VSRAB, \ 545 0xE77F) /* type = VRR_C VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */ \ 546 V(vpdi, VPDI, 0xE784) /* type = VRR_C VECTOR PERMUTE DOUBLEWORD IMMEDIATE */ \ 547 V(vpk, VPK, 0xE794) /* type = VRR_C VECTOR PACK */ \ 548 V(vmlh, VMLH, 0xE7A1) /* type = VRR_C VECTOR MULTIPLY LOGICAL HIGH */ \ 549 V(vml, VML, 0xE7A2) /* type = VRR_C VECTOR MULTIPLY LOW */ \ 550 V(vmh, VMH, 0xE7A3) /* type = VRR_C VECTOR MULTIPLY HIGH */ \ 551 V(vmle, VMLE, 0xE7A4) /* type = VRR_C VECTOR MULTIPLY LOGICAL EVEN */ \ 552 V(vmlo, VMLO, 0xE7A5) /* type = VRR_C VECTOR MULTIPLY LOGICAL ODD */ \ 553 V(vme, VME, 0xE7A6) /* type = VRR_C VECTOR MULTIPLY EVEN */ \ 554 V(vmo, VMO, 0xE7A7) /* type = VRR_C VECTOR MULTIPLY ODD */ \ 555 V(vgfm, VGFM, 0xE7B4) /* type = VRR_C VECTOR GALOIS FIELD MULTIPLY SUM */ \ 556 V(vfs, VFS, 0xE7E2) /* type = VRR_C VECTOR FP SUBTRACT */ \ 557 V(vfa, VFA, 0xE7E3) /* type = VRR_C VECTOR FP ADD */ \ 558 V(vfd, VFD, 0xE7E5) /* type = VRR_C VECTOR FP DIVIDE */ \ 559 V(vfm, VFM, 0xE7E7) /* type = VRR_C VECTOR FP MULTIPLY */ \ 560 V(vfce, VFCE, 0xE7E8) /* type = VRR_C VECTOR FP COMPARE EQUAL */ \ 561 V(vfche, VFCHE, 0xE7EA) /* type = VRR_C VECTOR FP COMPARE HIGH OR EQUAL */ \ 562 V(vfch, VFCH, 0xE7EB) /* type = VRR_C VECTOR FP COMPARE HIGH */ \ 563 V(vavgl, VAVGL, 0xE7F0) /* type = VRR_C VECTOR AVERAGE LOGICAL */ \ 564 V(vacc, VACC, 0xE7F1) /* type = VRR_C VECTOR ADD COMPUTE CARRY */ \ 565 V(vavg, VAVG, 0xE7F2) /* type = VRR_C VECTOR AVERAGE */ \ 566 V(va, VA, 0xE7F3) /* type = VRR_C VECTOR ADD */ \ 567 V(vscbi, VSCBI, \ 568 0xE7F5) /* type = VRR_C VECTOR SUBTRACT COMPUTE BORROW INDICATION */ \ 569 V(vs, VS, 0xE7F7) /* type = VRR_C VECTOR SUBTRACT */ \ 570 V(vmnl, VMNL, 0xE7FC) /* type = VRR_C VECTOR MINIMUM LOGICAL */ \ 571 V(vmxl, VMXL, 0xE7FD) /* type = VRR_C VECTOR MAXIMUM LOGICAL */ \ 572 V(vmn, VMN, 0xE7FE) /* type = VRR_C VECTOR MINIMUM */ \ 573 V(vmx, VMX, 0xE7FF) /* type = VRR_C VECTOR MAXIMUM */ 574 575 #define S390_VRI_A_OPCODE_LIST(V) \ 576 V(vleib, VLEIB, 0xE740) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (8) */ \ 577 V(vleih, VLEIH, \ 578 0xE741) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (16) */ \ 579 V(vleig, VLEIG, \ 580 0xE742) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (64) */ \ 581 V(vleif, VLEIF, \ 582 0xE743) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (32) */ \ 583 V(vgbm, VGBM, 0xE744) /* type = VRI_A VECTOR GENERATE BYTE MASK */ \ 584 V(vrepi, VREPI, 0xE745) /* type = VRI_A VECTOR REPLICATE IMMEDIATE */ 585 586 #define S390_VRR_D_OPCODE_LIST(V) \ 587 V(vstrc, VSTRC, 0xE78A) /* type = VRR_D VECTOR STRING RANGE COMPARE */ \ 588 V(vmalh, VMALH, \ 589 0xE7A9) /* type = VRR_D VECTOR MULTIPLY AND ADD LOGICAL HIGH */ \ 590 V(vmal, VMAL, 0xE7AA) /* type = VRR_D VECTOR MULTIPLY AND ADD LOW */ \ 591 V(vmah, VMAH, 0xE7AB) /* type = VRR_D VECTOR MULTIPLY AND ADD HIGH */ \ 592 V(vmale, VMALE, \ 593 0xE7AC) /* type = VRR_D VECTOR MULTIPLY AND ADD LOGICAL EVEN */ \ 594 V(vmalo, VMALO, \ 595 0xE7AD) /* type = VRR_D VECTOR MULTIPLY AND ADD LOGICAL ODD */ \ 596 V(vmae, VMAE, 0xE7AE) /* type = VRR_D VECTOR MULTIPLY AND ADD EVEN */ \ 597 V(vmao, VMAO, 0xE7AF) /* type = VRR_D VECTOR MULTIPLY AND ADD ODD */ \ 598 V(vaccc, VACCC, \ 599 0xE7B9) /* type = VRR_D VECTOR ADD WITH CARRY COMPUTE CARRY */ \ 600 V(vac, VAC, 0xE7BB) /* type = VRR_D VECTOR ADD WITH CARRY */ \ 601 V(vgfma, VGFMA, \ 602 0xE7BC) /* type = VRR_D VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */ \ 603 V(vsbcbi, VSBCBI, 0xE7BD) /* type = VRR_D VECTOR SUBTRACT WITH BORROW */ \ 604 /* COMPUTE BORROW INDICATION */ \ 605 V(vsbi, VSBI, \ 606 0xE7BF) /* type = VRR_D VECTOR SUBTRACT WITH BORROW INDICATION */ 607 608 #define S390_VRI_B_OPCODE_LIST(V) \ 609 V(vgm, VGM, 0xE746) /* type = VRI_B VECTOR GENERATE MASK */ 610 611 #define S390_VRR_E_OPCODE_LIST(V) \ 612 V(vperm, VPERM, 0xE78C) /* type = VRR_E VECTOR PERMUTE */ \ 613 V(vsel, VSEL, 0xE78D) /* type = VRR_E VECTOR SELECT */ \ 614 V(vfms, VFMS, 0xE78E) /* type = VRR_E VECTOR FP MULTIPLY AND SUBTRACT */ \ 615 V(vfma, VFMA, 0xE78F) /* type = VRR_E VECTOR FP MULTIPLY AND ADD */ 616 617 #define S390_VRI_C_OPCODE_LIST(V) \ 618 V(vrep, VREP, 0xE74D) /* type = VRI_C VECTOR REPLICATE */ 619 620 #define S390_VRI_D_OPCODE_LIST(V) \ 621 V(verim, VERIM, \ 622 0xE772) /* type = VRI_D VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */ \ 623 V(vsldb, VSLDB, 0xE777) /* type = VRI_D VECTOR SHIFT LEFT DOUBLE BY BYTE */ 624 625 #define S390_VRR_F_OPCODE_LIST(V) \ 626 V(vlvgp, VLVGP, 0xE762) /* type = VRR_F VECTOR LOAD VR FROM GRS DISJOINT */ 627 628 #define S390_RIS_OPCODE_LIST(V) \ 629 V(cgib, CGIB, \ 630 0xECFC) /* type = RIS COMPARE IMMEDIATE AND BRANCH (64<-8) */ \ 631 V(clgib, CLGIB, \ 632 0xECFD) /* type = RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) */ \ 633 V(cib, CIB, 0xECFE) /* type = RIS COMPARE IMMEDIATE AND BRANCH (32<-8) */ \ 634 V(clib, CLIB, \ 635 0xECFF) /* type = RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) */ 636 637 #define S390_VRI_E_OPCODE_LIST(V) \ 638 V(vftci, VFTCI, \ 639 0xE74A) /* type = VRI_E VECTOR FP TEST DATA CLASS IMMEDIATE */ 640 641 #define S390_RSL_A_OPCODE_LIST(V) \ 642 V(tp, TP, 0xEBC0) /* type = RSL_A TEST DECIMAL */ 643 644 #define S390_RSL_B_OPCODE_LIST(V) \ 645 V(cpdt, CPDT, 0xEDAC) /* type = RSL_B CONVERT TO PACKED (from long DFP) */ \ 646 V(cpxt, CPXT, \ 647 0xEDAD) /* type = RSL_B CONVERT TO PACKED (from extended DFP) */ \ 648 V(cdpt, CDPT, 0xEDAE) /* type = RSL_B CONVERT FROM PACKED (to long DFP) */ \ 649 V(cxpt, CXPT, \ 650 0xEDAF) /* type = RSL_B CONVERT FROM PACKED (to extended DFP) */ \ 651 V(czdt, CZDT, 0xEDA8) /* type = RSL CONVERT TO ZONED (from long DFP) */ \ 652 V(czxt, CZXT, 0xEDA9) /* type = RSL CONVERT TO ZONED (from extended DFP) */ \ 653 V(cdzt, CDZT, 0xEDAA) /* type = RSL CONVERT FROM ZONED (to long DFP) */ \ 654 V(cxzt, CXZT, 0xEDAB) /* type = RSL CONVERT FROM ZONED (to extended DFP) */ 655 656 #define S390_SI_OPCODE_LIST(V) \ 657 V(tm, TM, 0x91) /* type = SI TEST UNDER MASK */ \ 658 V(mvi, MVI, 0x92) /* type = SI MOVE (immediate) */ \ 659 V(ni, NI, 0x94) /* type = SI AND (immediate) */ \ 660 V(cli, CLI, 0x95) /* type = SI COMPARE LOGICAL (immediate) */ \ 661 V(oi, OI, 0x96) /* type = SI OR (immediate) */ \ 662 V(xi, XI, 0x97) /* type = SI EXCLUSIVE OR (immediate) */ \ 663 V(stnsm, STNSM, 0xAC) /* type = SI STORE THEN AND SYSTEM MASK */ \ 664 V(stosm, STOSM, 0xAD) /* type = SI STORE THEN OR SYSTEM MASK */ \ 665 V(mc, MC, 0xAF) /* type = SI MONITOR CALL */ 666 667 #define S390_SIL_OPCODE_LIST(V) \ 668 V(mvhhi, MVHHI, 0xE544) /* type = SIL MOVE (16<-16) */ \ 669 V(mvghi, MVGHI, 0xE548) /* type = SIL MOVE (64<-16) */ \ 670 V(mvhi, MVHI, 0xE54C) /* type = SIL MOVE (32<-16) */ \ 671 V(chhsi, CHHSI, \ 672 0xE554) /* type = SIL COMPARE HALFWORD IMMEDIATE (16<-16) */ \ 673 V(clhhsi, CLHHSI, \ 674 0xE555) /* type = SIL COMPARE LOGICAL IMMEDIATE (16<-16) */ \ 675 V(cghsi, CGHSI, \ 676 0xE558) /* type = SIL COMPARE HALFWORD IMMEDIATE (64<-16) */ \ 677 V(clghsi, CLGHSI, \ 678 0xE559) /* type = SIL COMPARE LOGICAL IMMEDIATE (64<-16) */ \ 679 V(chsi, CHSI, 0xE55C) /* type = SIL COMPARE HALFWORD IMMEDIATE (32<-16) */ \ 680 V(clfhsi, CLFHSI, \ 681 0xE55D) /* type = SIL COMPARE LOGICAL IMMEDIATE (32<-16) */ \ 682 V(tbegin, TBEGIN, \ 683 0xE560) /* type = SIL TRANSACTION BEGIN (nonconstrained) */ \ 684 V(tbeginc, TBEGINC, \ 685 0xE561) /* type = SIL TRANSACTION BEGIN (constrained) */ 686 687 #define S390_VRS_A_OPCODE_LIST(V) \ 688 V(vesl, VESL, 0xE730) /* type = VRS_A VECTOR ELEMENT SHIFT LEFT */ \ 689 V(verll, VERLL, \ 690 0xE733) /* type = VRS_A VECTOR ELEMENT ROTATE LEFT LOGICAL */ \ 691 V(vlm, VLM, 0xE736) /* type = VRS_A VECTOR LOAD MULTIPLE */ \ 692 V(vesrl, VESRL, \ 693 0xE738) /* type = VRS_A VECTOR ELEMENT SHIFT RIGHT LOGICAL */ \ 694 V(vesra, VESRA, \ 695 0xE73A) /* type = VRS_A VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ \ 696 V(vstm, VSTM, 0xE73E) /* type = VRS_A VECTOR STORE MULTIPLE */ 697 698 #define S390_RIL_A_OPCODE_LIST(V) \ 699 V(lgfi, LGFI, 0xC01) /* type = RIL_A LOAD IMMEDIATE (64<-32) */ \ 700 V(xihf, XIHF, 0xC06) /* type = RIL_A EXCLUSIVE OR IMMEDIATE (high) */ \ 701 V(xilf, XILF, 0xC07) /* type = RIL_A EXCLUSIVE OR IMMEDIATE (low) */ \ 702 V(iihf, IIHF, 0xC08) /* type = RIL_A INSERT IMMEDIATE (high) */ \ 703 V(iilf, IILF, 0xC09) /* type = RIL_A INSERT IMMEDIATE (low) */ \ 704 V(nihf, NIHF, 0xC0A) /* type = RIL_A AND IMMEDIATE (high) */ \ 705 V(nilf, NILF, 0xC0B) /* type = RIL_A AND IMMEDIATE (low) */ \ 706 V(oihf, OIHF, 0xC0C) /* type = RIL_A OR IMMEDIATE (high) */ \ 707 V(oilf, OILF, 0xC0D) /* type = RIL_A OR IMMEDIATE (low) */ \ 708 V(llihf, LLIHF, 0xC0E) /* type = RIL_A LOAD LOGICAL IMMEDIATE (high) */ \ 709 V(llilf, LLILF, 0xC0F) /* type = RIL_A LOAD LOGICAL IMMEDIATE (low) */ \ 710 V(msgfi, MSGFI, 0xC20) /* type = RIL_A MULTIPLY SINGLE IMMEDIATE (64<-32) */ \ 711 V(msfi, MSFI, 0xC21) /* type = RIL_A MULTIPLY SINGLE IMMEDIATE (32) */ \ 712 V(slgfi, SLGFI, \ 713 0xC24) /* type = RIL_A SUBTRACT LOGICAL IMMEDIATE (64<-32) */ \ 714 V(slfi, SLFI, 0xC25) /* type = RIL_A SUBTRACT LOGICAL IMMEDIATE (32) */ \ 715 V(agfi, AGFI, 0xC28) /* type = RIL_A ADD IMMEDIATE (64<-32) */ \ 716 V(afi, AFI, 0xC29) /* type = RIL_A ADD IMMEDIATE (32) */ \ 717 V(algfi, ALGFI, 0xC2A) /* type = RIL_A ADD LOGICAL IMMEDIATE (64<-32) */ \ 718 V(alfi, ALFI, 0xC2B) /* type = RIL_A ADD LOGICAL IMMEDIATE (32) */ \ 719 V(cgfi, CGFI, 0xC2C) /* type = RIL_A COMPARE IMMEDIATE (64<-32) */ \ 720 V(cfi, CFI, 0xC2D) /* type = RIL_A COMPARE IMMEDIATE (32) */ \ 721 V(clgfi, CLGFI, 0xC2E) /* type = RIL_A COMPARE LOGICAL IMMEDIATE (64<-32) */ \ 722 V(clfi, CLFI, 0xC2F) /* type = RIL_A COMPARE LOGICAL IMMEDIATE (32) */ \ 723 V(aih, AIH, 0xCC8) /* type = RIL_A ADD IMMEDIATE HIGH (32) */ \ 724 V(alsih, ALSIH, \ 725 0xCCA) /* type = RIL_A ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) */ \ 726 V(alsihn, ALSIHN, \ 727 0xCCB) /* type = RIL_A ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) */ \ 728 V(cih, CIH, 0xCCD) /* type = RIL_A COMPARE IMMEDIATE HIGH (32) */ \ 729 V(clih, CLIH, 0xCCF) /* type = RIL_A COMPARE LOGICAL IMMEDIATE HIGH (32) */ 730 731 #define S390_RIL_B_OPCODE_LIST(V) \ 732 V(larl, LARL, 0xC00) /* type = RIL_B LOAD ADDRESS RELATIVE LONG */ \ 733 V(brasl, BRASL, 0xC05) /* type = RIL_B BRANCH RELATIVE AND SAVE LONG */ \ 734 V(llhrl, LLHRL, \ 735 0xC42) /* type = RIL_B LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) */ \ 736 V(lghrl, LGHRL, \ 737 0xC44) /* type = RIL_B LOAD HALFWORD RELATIVE LONG (64<-16) */ \ 738 V(lhrl, LHRL, 0xC45) /* type = RIL_B LOAD HALFWORD RELATIVE LONG (32<-16) */ \ 739 V(llghrl, LLGHRL, \ 740 0xC46) /* type = RIL_B LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) */ \ 741 V(sthrl, STHRL, 0xC47) /* type = RIL_B STORE HALFWORD RELATIVE LONG (16) */ \ 742 V(lgrl, LGRL, 0xC48) /* type = RIL_B LOAD RELATIVE LONG (64) */ \ 743 V(stgrl, STGRL, 0xC4B) /* type = RIL_B STORE RELATIVE LONG (64) */ \ 744 V(lgfrl, LGFRL, 0xC4C) /* type = RIL_B LOAD RELATIVE LONG (64<-32) */ \ 745 V(lrl, LRL, 0xC4D) /* type = RIL_B LOAD RELATIVE LONG (32) */ \ 746 V(llgfrl, LLGFRL, \ 747 0xC4E) /* type = RIL_B LOAD LOGICAL RELATIVE LONG (64<-32) */ \ 748 V(strl, STRL, 0xC4F) /* type = RIL_B STORE RELATIVE LONG (32) */ \ 749 V(exrl, EXRL, 0xC60) /* type = RIL_B EXECUTE RELATIVE LONG */ \ 750 V(cghrl, CGHRL, \ 751 0xC64) /* type = RIL_B COMPARE HALFWORD RELATIVE LONG (64<-16) */ \ 752 V(chrl, CHRL, \ 753 0xC65) /* type = RIL_B COMPARE HALFWORD RELATIVE LONG (32<-16) */ \ 754 V(clghrl, CLGHRL, \ 755 0xC66) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (64<-16) */ \ 756 V(clhrl, CLHRL, \ 757 0xC67) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (32<-16) */ \ 758 V(cgrl, CGRL, 0xC68) /* type = RIL_B COMPARE RELATIVE LONG (64) */ \ 759 V(clgrl, CLGRL, 0xC6A) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (64) */ \ 760 V(cgfrl, CGFRL, 0xC6C) /* type = RIL_B COMPARE RELATIVE LONG (64<-32) */ \ 761 V(crl, CRL, 0xC6D) /* type = RIL_B COMPARE RELATIVE LONG (32) */ \ 762 V(clgfrl, CLGFRL, \ 763 0xC6E) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (64<-32) */ \ 764 V(clrl, CLRL, 0xC6F) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (32) */ \ 765 V(brcth, BRCTH, 0xCC6) /* type = RIL_B BRANCH RELATIVE ON COUNT HIGH (32) */ 766 767 #define S390_VRS_B_OPCODE_LIST(V) \ 768 V(vlvg, VLVG, 0xE722) /* type = VRS_B VECTOR LOAD VR ELEMENT FROM GR */ \ 769 V(vll, VLL, 0xE737) /* type = VRS_B VECTOR LOAD WITH LENGTH */ \ 770 V(vstl, VSTL, 0xE73F) /* type = VRS_B VECTOR STORE WITH LENGTH */ 771 772 #define S390_RIL_C_OPCODE_LIST(V) \ 773 V(brcl, BRCL, 0xC04) /* type = RIL_C BRANCH RELATIVE ON CONDITION LONG */ \ 774 V(pfdrl, PFDRL, 0xC62) /* type = RIL_C PREFETCH DATA RELATIVE LONG */ 775 776 #define S390_VRS_C_OPCODE_LIST(V) \ 777 V(vlgv, VLGV, 0xE721) /* type = VRS_C VECTOR LOAD GR FROM VR ELEMENT */ 778 779 #define S390_RI_A_OPCODE_LIST(V) \ 780 V(iihh, IIHH, 0xA50) /* type = RI_A INSERT IMMEDIATE (high high) */ \ 781 V(iihl, IIHL, 0xA51) /* type = RI_A INSERT IMMEDIATE (high low) */ \ 782 V(iilh, IILH, 0xA52) /* type = RI_A INSERT IMMEDIATE (low high) */ \ 783 V(iill, IILL, 0xA53) /* type = RI_A INSERT IMMEDIATE (low low) */ \ 784 V(nihh, NIHH, 0xA54) /* type = RI_A AND IMMEDIATE (high high) */ \ 785 V(nihl, NIHL, 0xA55) /* type = RI_A AND IMMEDIATE (high low) */ \ 786 V(nilh, NILH, 0xA56) /* type = RI_A AND IMMEDIATE (low high) */ \ 787 V(nill, NILL, 0xA57) /* type = RI_A AND IMMEDIATE (low low) */ \ 788 V(oihh, OIHH, 0xA58) /* type = RI_A OR IMMEDIATE (high high) */ \ 789 V(oihl, OIHL, 0xA59) /* type = RI_A OR IMMEDIATE (high low) */ \ 790 V(oilh, OILH, 0xA5A) /* type = RI_A OR IMMEDIATE (low high) */ \ 791 V(oill, OILL, 0xA5B) /* type = RI_A OR IMMEDIATE (low low) */ \ 792 V(llihh, LLIHH, 0xA5C) /* type = RI_A LOAD LOGICAL IMMEDIATE (high high) */ \ 793 V(llihl, LLIHL, 0xA5D) /* type = RI_A LOAD LOGICAL IMMEDIATE (high low) */ \ 794 V(llilh, LLILH, 0xA5E) /* type = RI_A LOAD LOGICAL IMMEDIATE (low high) */ \ 795 V(llill, LLILL, 0xA5F) /* type = RI_A LOAD LOGICAL IMMEDIATE (low low) */ \ 796 V(tmlh, TMLH, 0xA70) /* type = RI_A TEST UNDER MASK (low high) */ \ 797 V(tmll, TMLL, 0xA71) /* type = RI_A TEST UNDER MASK (low low) */ \ 798 V(tmhh, TMHH, 0xA72) /* type = RI_A TEST UNDER MASK (high high) */ \ 799 V(tmhl, TMHL, 0xA73) /* type = RI_A TEST UNDER MASK (high low) */ \ 800 V(lhi, LHI, 0xA78) /* type = RI_A LOAD HALFWORD IMMEDIATE (32)<-16 */ \ 801 V(lghi, LGHI, 0xA79) /* type = RI_A LOAD HALFWORD IMMEDIATE (64<-16) */ \ 802 V(ahi, AHI, 0xA7A) /* type = RI_A ADD HALFWORD IMMEDIATE (32<-16) */ \ 803 V(aghi, AGHI, 0xA7B) /* type = RI_A ADD HALFWORD IMMEDIATE (64<-16) */ \ 804 V(mhi, MHI, 0xA7C) /* type = RI_A MULTIPLY HALFWORD IMMEDIATE (32<-16) */ \ 805 V(mghi, MGHI, 0xA7D) /* type = RI_A MULTIPLY HALFWORD IMMEDIATE (64<-16) */ \ 806 V(chi, CHI, 0xA7E) /* type = RI_A COMPARE HALFWORD IMMEDIATE (32<-16) */ \ 807 V(cghi, CGHI, 0xA7F) /* type = RI_A COMPARE HALFWORD IMMEDIATE (64<-16) */ 808 809 #define S390_RSI_OPCODE_LIST(V) \ 810 V(brxh, BRXH, 0x84) /* type = RSI BRANCH RELATIVE ON INDEX HIGH (32) */ \ 811 V(brxle, BRXLE, \ 812 0x85) /* type = RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) */ 813 814 #define S390_RI_B_OPCODE_LIST(V) \ 815 V(bras, BRAS, 0xA75) /* type = RI_B BRANCH RELATIVE AND SAVE */ \ 816 V(brct, BRCT, 0xA76) /* type = RI_B BRANCH RELATIVE ON COUNT (32) */ \ 817 V(brctg, BRCTG, 0xA77) /* type = RI_B BRANCH RELATIVE ON COUNT (64) */ 818 819 #define S390_RI_C_OPCODE_LIST(V) \ 820 V(brc, BRC, 0xA74) /* type = RI_C BRANCH RELATIVE ON CONDITION */ 821 822 #define S390_SMI_OPCODE_LIST(V) \ 823 V(bpp, BPP, 0xC7) /* type = SMI BRANCH PREDICTION PRELOAD */ 824 825 #define S390_RXY_A_OPCODE_LIST(V) \ 826 V(ltg, LTG, 0xE302) /* type = RXY_A LOAD AND TEST (64) */ \ 827 V(lrag, LRAG, 0xE303) /* type = RXY_A LOAD REAL ADDRESS (64) */ \ 828 V(lg, LG, 0xE304) /* type = RXY_A LOAD (64) */ \ 829 V(cvby, CVBY, 0xE306) /* type = RXY_A CONVERT TO BINARY (32) */ \ 830 V(ag, AG, 0xE308) /* type = RXY_A ADD (64) */ \ 831 V(sg, SG, 0xE309) /* type = RXY_A SUBTRACT (64) */ \ 832 V(alg, ALG, 0xE30A) /* type = RXY_A ADD LOGICAL (64) */ \ 833 V(slg, SLG, 0xE30B) /* type = RXY_A SUBTRACT LOGICAL (64) */ \ 834 V(msg, MSG, 0xE30C) /* type = RXY_A MULTIPLY SINGLE (64) */ \ 835 V(dsg, DSG, 0xE30D) /* type = RXY_A DIVIDE SINGLE (64) */ \ 836 V(cvbg, CVBG, 0xE30E) /* type = RXY_A CONVERT TO BINARY (64) */ \ 837 V(lrvg, LRVG, 0xE30F) /* type = RXY_A LOAD REVERSED (64) */ \ 838 V(lt_z, LT, 0xE312) /* type = RXY_A LOAD AND TEST (32) */ \ 839 V(lray, LRAY, 0xE313) /* type = RXY_A LOAD REAL ADDRESS (32) */ \ 840 V(lgf, LGF, 0xE314) /* type = RXY_A LOAD (64<-32) */ \ 841 V(lgh, LGH, 0xE315) /* type = RXY_A LOAD HALFWORD (64<-16) */ \ 842 V(llgf, LLGF, 0xE316) /* type = RXY_A LOAD LOGICAL (64<-32) */ \ 843 V(llgt, LLGT, \ 844 0xE317) /* type = RXY_A LOAD LOGICAL THIRTY ONE BITS (64<-31) */ \ 845 V(agf, AGF, 0xE318) /* type = RXY_A ADD (64<-32) */ \ 846 V(sgf, SGF, 0xE319) /* type = RXY_A SUBTRACT (64<-32) */ \ 847 V(algf, ALGF, 0xE31A) /* type = RXY_A ADD LOGICAL (64<-32) */ \ 848 V(slgf, SLGF, 0xE31B) /* type = RXY_A SUBTRACT LOGICAL (64<-32) */ \ 849 V(msgf, MSGF, 0xE31C) /* type = RXY_A MULTIPLY SINGLE (64<-32) */ \ 850 V(dsgf, DSGF, 0xE31D) /* type = RXY_A DIVIDE SINGLE (64<-32) */ \ 851 V(lrv, LRV, 0xE31E) /* type = RXY_A LOAD REVERSED (32) */ \ 852 V(lrvh, LRVH, 0xE31F) /* type = RXY_A LOAD REVERSED (16) */ \ 853 V(cg, CG, 0xE320) /* type = RXY_A COMPARE (64) */ \ 854 V(clg, CLG, 0xE321) /* type = RXY_A COMPARE LOGICAL (64) */ \ 855 V(stg, STG, 0xE324) /* type = RXY_A STORE (64) */ \ 856 V(ntstg, NTSTG, 0xE325) /* type = RXY_A NONTRANSACTIONAL STORE (64) */ \ 857 V(cvdy, CVDY, 0xE326) /* type = RXY_A CONVERT TO DECIMAL (32) */ \ 858 V(lzrg, LZRG, 0xE32A) /* type = RXY_A LOAD AND ZERO RIGHTMOST BYTE (64) */ \ 859 V(cvdg, CVDG, 0xE32E) /* type = RXY_A CONVERT TO DECIMAL (64) */ \ 860 V(strvg, STRVG, 0xE32F) /* type = RXY_A STORE REVERSED (64) */ \ 861 V(cgf, CGF, 0xE330) /* type = RXY_A COMPARE (64<-32) */ \ 862 V(clgf, CLGF, 0xE331) /* type = RXY_A COMPARE LOGICAL (64<-32) */ \ 863 V(ltgf, LTGF, 0xE332) /* type = RXY_A LOAD AND TEST (64<-32) */ \ 864 V(cgh, CGH, 0xE334) /* type = RXY_A COMPARE HALFWORD (64<-16) */ \ 865 V(llzrgf, LLZRGF, \ 866 0xE33A) /* type = RXY_A LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64<-32) */ \ 867 V(lzrf, LZRF, 0xE33B) /* type = RXY_A LOAD AND ZERO RIGHTMOST BYTE (32) */ \ 868 V(strv, STRV, 0xE33E) /* type = RXY_A STORE REVERSED (32) */ \ 869 V(strvh, STRVH, 0xE33F) /* type = RXY_A STORE REVERSED (16) */ \ 870 V(bctg, BCTG, 0xE346) /* type = RXY_A BRANCH ON COUNT (64) */ \ 871 V(sty, STY, 0xE350) /* type = RXY_A STORE (32) */ \ 872 V(msy, MSY, 0xE351) /* type = RXY_A MULTIPLY SINGLE (32) */ \ 873 V(ny, NY, 0xE354) /* type = RXY_A AND (32) */ \ 874 V(cly, CLY, 0xE355) /* type = RXY_A COMPARE LOGICAL (32) */ \ 875 V(oy, OY, 0xE356) /* type = RXY_A OR (32) */ \ 876 V(xy, XY, 0xE357) /* type = RXY_A EXCLUSIVE OR (32) */ \ 877 V(ly, LY, 0xE358) /* type = RXY_A LOAD (32) */ \ 878 V(cy, CY, 0xE359) /* type = RXY_A COMPARE (32) */ \ 879 V(ay, AY, 0xE35A) /* type = RXY_A ADD (32) */ \ 880 V(sy, SY, 0xE35B) /* type = RXY_A SUBTRACT (32) */ \ 881 V(mfy, MFY, 0xE35C) /* type = RXY_A MULTIPLY (64<-32) */ \ 882 V(aly, ALY, 0xE35E) /* type = RXY_A ADD LOGICAL (32) */ \ 883 V(sly, SLY, 0xE35F) /* type = RXY_A SUBTRACT LOGICAL (32) */ \ 884 V(sthy, STHY, 0xE370) /* type = RXY_A STORE HALFWORD (16) */ \ 885 V(lay, LAY, 0xE371) /* type = RXY_A LOAD ADDRESS */ \ 886 V(stcy, STCY, 0xE372) /* type = RXY_A STORE CHARACTER */ \ 887 V(icy, ICY, 0xE373) /* type = RXY_A INSERT CHARACTER */ \ 888 V(laey, LAEY, 0xE375) /* type = RXY_A LOAD ADDRESS EXTENDED */ \ 889 V(lb, LB, 0xE376) /* type = RXY_A LOAD BYTE (32<-8) */ \ 890 V(lgb, LGB, 0xE377) /* type = RXY_A LOAD BYTE (64<-8) */ \ 891 V(lhy, LHY, 0xE378) /* type = RXY_A LOAD HALFWORD (32)<-16 */ \ 892 V(chy, CHY, 0xE379) /* type = RXY_A COMPARE HALFWORD (32<-16) */ \ 893 V(ahy, AHY, 0xE37A) /* type = RXY_A ADD HALFWORD (32<-16) */ \ 894 V(shy, SHY, 0xE37B) /* type = RXY_A SUBTRACT HALFWORD (32<-16) */ \ 895 V(mhy, MHY, 0xE37C) /* type = RXY_A MULTIPLY HALFWORD (32<-16) */ \ 896 V(ng, NG, 0xE380) /* type = RXY_A AND (64) */ \ 897 V(og, OG, 0xE381) /* type = RXY_A OR (64) */ \ 898 V(xg, XG, 0xE382) /* type = RXY_A EXCLUSIVE OR (64) */ \ 899 V(lgat, LGAT, 0xE385) /* type = RXY_A LOAD AND TRAP (64) */ \ 900 V(mlg, MLG, 0xE386) /* type = RXY_A MULTIPLY LOGICAL (128<-64) */ \ 901 V(dlg, DLG, 0xE387) /* type = RXY_A DIVIDE LOGICAL (64<-128) */ \ 902 V(alcg, ALCG, 0xE388) /* type = RXY_A ADD LOGICAL WITH CARRY (64) */ \ 903 V(slbg, SLBG, 0xE389) /* type = RXY_A SUBTRACT LOGICAL WITH BORROW (64) */ \ 904 V(stpq, STPQ, 0xE38E) /* type = RXY_A STORE PAIR TO QUADWORD */ \ 905 V(lpq, LPQ, 0xE38F) /* type = RXY_A LOAD PAIR FROM QUADWORD (64&64<-128) */ \ 906 V(llgc, LLGC, 0xE390) /* type = RXY_A LOAD LOGICAL CHARACTER (64<-8) */ \ 907 V(llgh, LLGH, 0xE391) /* type = RXY_A LOAD LOGICAL HALFWORD (64<-16) */ \ 908 V(llc, LLC, 0xE394) /* type = RXY_A LOAD LOGICAL CHARACTER (32<-8) */ \ 909 V(llh, LLH, 0xE395) /* type = RXY_A LOAD LOGICAL HALFWORD (32<-16) */ \ 910 V(ml, ML, 0xE396) /* type = RXY_A MULTIPLY LOGICAL (64<-32) */ \ 911 V(dl, DL, 0xE397) /* type = RXY_A DIVIDE LOGICAL (32<-64) */ \ 912 V(alc, ALC, 0xE398) /* type = RXY_A ADD LOGICAL WITH CARRY (32) */ \ 913 V(slb, SLB, 0xE399) /* type = RXY_A SUBTRACT LOGICAL WITH BORROW (32) */ \ 914 V(llgtat, LLGTAT, \ 915 0xE39C) /* type = RXY_A LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) */ \ 916 V(llgfat, LLGFAT, 0xE39D) /* type = RXY_A LOAD LOGICAL AND TRAP (64<-32) */ \ 917 V(lat, LAT, 0xE39F) /* type = RXY_A LOAD AND TRAP (32L<-32) */ \ 918 V(lbh, LBH, 0xE3C0) /* type = RXY_A LOAD BYTE HIGH (32<-8) */ \ 919 V(llch, LLCH, 0xE3C2) /* type = RXY_A LOAD LOGICAL CHARACTER HIGH (32<-8) */ \ 920 V(stch, STCH, 0xE3C3) /* type = RXY_A STORE CHARACTER HIGH (8) */ \ 921 V(lhh, LHH, 0xE3C4) /* type = RXY_A LOAD HALFWORD HIGH (32<-16) */ \ 922 V(llhh, LLHH, 0xE3C6) /* type = RXY_A LOAD LOGICAL HALFWORD HIGH (32<-16) */ \ 923 V(sthh, STHH, 0xE3C7) /* type = RXY_A STORE HALFWORD HIGH (16) */ \ 924 V(lfhat, LFHAT, 0xE3C8) /* type = RXY_A LOAD HIGH AND TRAP (32H<-32) */ \ 925 V(lfh, LFH, 0xE3CA) /* type = RXY_A LOAD HIGH (32) */ \ 926 V(stfh, STFH, 0xE3CB) /* type = RXY_A STORE HIGH (32) */ \ 927 V(chf, CHF, 0xE3CD) /* type = RXY_A COMPARE HIGH (32) */ \ 928 V(clhf, CLHF, 0xE3CF) /* type = RXY_A COMPARE LOGICAL HIGH (32) */ \ 929 V(ley, LEY, 0xED64) /* type = RXY_A LOAD (short) */ \ 930 V(ldy, LDY, 0xED65) /* type = RXY_A LOAD (long) */ \ 931 V(stey, STEY, 0xED66) /* type = RXY_A STORE (short) */ \ 932 V(stdy, STDY, 0xED67) /* type = RXY_A STORE (long) */ \ 933 V(msc, MSC, 0xE353) /* type = RSY_A MULTIPLY SINGLE (32) */ \ 934 V(msgc, MSGC, 0xE383) /* type = RSY_A MULTIPLY SINGLE (64) */ 935 936 #define S390_RXY_B_OPCODE_LIST(V) \ 937 V(pfd, PFD, 0xE336) /* type = RXY_B PREFETCH DATA */ 938 939 #define S390_SIY_OPCODE_LIST(V) \ 940 V(tmy, TMY, 0xEB51) /* type = SIY TEST UNDER MASK */ \ 941 V(mviy, MVIY, 0xEB52) /* type = SIY MOVE (immediate) */ \ 942 V(niy, NIY, 0xEB54) /* type = SIY AND (immediate) */ \ 943 V(cliy, CLIY, 0xEB55) /* type = SIY COMPARE LOGICAL (immediate) */ \ 944 V(oiy, OIY, 0xEB56) /* type = SIY OR (immediate) */ \ 945 V(xiy, XIY, 0xEB57) /* type = SIY EXCLUSIVE OR (immediate) */ \ 946 V(asi, ASI, 0xEB6A) /* type = SIY ADD IMMEDIATE (32<-8) */ \ 947 V(alsi, ALSI, \ 948 0xEB6E) /* type = SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) */ \ 949 V(agsi, AGSI, 0xEB7A) /* type = SIY ADD IMMEDIATE (64<-8) */ \ 950 V(algsi, ALGSI, \ 951 0xEB7E) /* type = SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) */ 952 953 #define S390_SS_A_OPCODE_LIST(V) \ 954 V(trtr, TRTR, 0xD0) /* type = SS_A TRANSLATE AND TEST REVERSE */ \ 955 V(mvn, MVN, 0xD1) /* type = SS_A MOVE NUMERICS */ \ 956 V(mvc, MVC, 0xD2) /* type = SS_A MOVE (character) */ \ 957 V(mvz, MVZ, 0xD3) /* type = SS_A MOVE ZONES */ \ 958 V(nc, NC, 0xD4) /* type = SS_A AND (character) */ \ 959 V(clc, CLC, 0xD5) /* type = SS_A COMPARE LOGICAL (character) */ \ 960 V(oc, OC, 0xD6) /* type = SS_A OR (character) */ \ 961 V(xc, XC, 0xD7) /* type = SS_A EXCLUSIVE OR (character) */ \ 962 V(tr, TR, 0xDC) /* type = SS_A TRANSLATE */ \ 963 V(trt, TRT, 0xDD) /* type = SS_A TRANSLATE AND TEST */ \ 964 V(ed, ED, 0xDE) /* type = SS_A EDIT */ \ 965 V(edmk, EDMK, 0xDF) /* type = SS_A EDIT AND MARK */ \ 966 V(unpku, UNPKU, 0xE2) /* type = SS_A UNPACK UNICODE */ \ 967 V(mvcin, MVCIN, 0xE8) /* type = SS_A MOVE INVERSE */ \ 968 V(unpka, UNPKA, 0xEA) /* type = SS_A UNPACK ASCII */ 969 970 #define S390_E_OPCODE_LIST(V) \ 971 V(pr, PR, 0x0101) /* type = E PROGRAM RETURN */ \ 972 V(upt, UPT, 0x0102) /* type = E UPDATE TREE */ \ 973 V(ptff, PTFF, 0x0104) /* type = E PERFORM TIMING FACILITY FUNCTION */ \ 974 V(sckpf, SCKPF, 0x0107) /* type = E SET CLOCK PROGRAMMABLE FIELD */ \ 975 V(pfpo, PFPO, 0x010A) /* type = E PERFORM FLOATING-POINT OPERATION */ \ 976 V(tam, TAM, 0x010B) /* type = E TEST ADDRESSING MODE */ \ 977 V(sam24, SAM24, 0x010C) /* type = E SET ADDRESSING MODE (24) */ \ 978 V(sam31, SAM31, 0x010D) /* type = E SET ADDRESSING MODE (31) */ \ 979 V(sam64, SAM64, 0x010E) /* type = E SET ADDRESSING MODE (64) */ \ 980 V(trap2, TRAP2, 0x01FF) /* type = E TRAP */ 981 982 #define S390_SS_B_OPCODE_LIST(V) \ 983 V(mvo, MVO, 0xF1) /* type = SS_B MOVE WITH OFFSET */ \ 984 V(pack, PACK, 0xF2) /* type = SS_B PACK */ \ 985 V(unpk, UNPK, 0xF3) /* type = SS_B UNPACK */ \ 986 V(zap, ZAP, 0xF8) /* type = SS_B ZERO AND ADD */ \ 987 V(cp, CP, 0xF9) /* type = SS_B COMPARE DECIMAL */ \ 988 V(ap, AP, 0xFA) /* type = SS_B ADD DECIMAL */ \ 989 V(sp, SP, 0xFB) /* type = SS_B SUBTRACT DECIMAL */ \ 990 V(mp, MP, 0xFC) /* type = SS_B MULTIPLY DECIMAL */ \ 991 V(dp, DP, 0xFD) /* type = SS_B DIVIDE DECIMAL */ 992 993 #define S390_SS_C_OPCODE_LIST(V) \ 994 V(srp, SRP, 0xF0) /* type = SS_C SHIFT AND ROUND DECIMAL */ 995 996 #define S390_SS_D_OPCODE_LIST(V) \ 997 V(mvck, MVCK, 0xD9) /* type = SS_D MOVE WITH KEY */ \ 998 V(mvcp, MVCP, 0xDA) /* type = SS_D MOVE TO PRIMARY */ \ 999 V(mvcs, MVCS, 0xDB) /* type = SS_D MOVE TO SECONDARY */ 1000 1001 #define S390_SS_E_OPCODE_LIST(V) \ 1002 V(plo, PLO, 0xEE) /* type = SS_E PERFORM LOCKED OPERATION */ \ 1003 V(lmd, LMD, 0xEF) /* type = SS_E LOAD MULTIPLE DISJOINT (64<-32&32) */ 1004 1005 #define S390_I_OPCODE_LIST(V) \ 1006 V(svc, SVC, 0x0A) /* type = I SUPERVISOR CALL */ 1007 1008 #define S390_SS_F_OPCODE_LIST(V) \ 1009 V(pku, PKU, 0xE1) /* type = SS_F PACK UNICODE */ \ 1010 V(pka, PKA, 0xE9) /* type = SS_F PACK ASCII */ 1011 1012 #define S390_SSE_OPCODE_LIST(V) \ 1013 V(lasp, LASP, 0xE500) /* type = SSE LOAD ADDRESS SPACE PARAMETERS */ \ 1014 V(tprot, TPROT, 0xE501) /* type = SSE TEST PROTECTION */ \ 1015 V(strag, STRAG, 0xE502) /* type = SSE STORE REAL ADDRESS */ \ 1016 V(mvcsk, MVCSK, 0xE50E) /* type = SSE MOVE WITH SOURCE KEY */ \ 1017 V(mvcdk, MVCDK, 0xE50F) /* type = SSE MOVE WITH DESTINATION KEY */ 1018 1019 #define S390_SSF_OPCODE_LIST(V) \ 1020 V(mvcos, MVCOS, 0xC80) /* type = SSF MOVE WITH OPTIONAL SPECIFICATIONS */ \ 1021 V(ectg, ECTG, 0xC81) /* type = SSF EXTRACT CPU TIME */ \ 1022 V(csst, CSST, 0xC82) /* type = SSF COMPARE AND SWAP AND STORE */ \ 1023 V(lpd, LPD, 0xC84) /* type = SSF LOAD PAIR DISJOINT (32) */ \ 1024 V(lpdg, LPDG, 0xC85) /* type = SSF LOAD PAIR DISJOINT (64) */ 1025 1026 #define S390_RS_A_OPCODE_LIST(V) \ 1027 V(bxh, BXH, 0x86) /* type = RS_A BRANCH ON INDEX HIGH (32) */ \ 1028 V(bxle, BXLE, 0x87) /* type = RS_A BRANCH ON INDEX LOW OR EQUAL (32) */ \ 1029 V(srl, SRL, 0x88) /* type = RS_A SHIFT RIGHT SINGLE LOGICAL (32) */ \ 1030 V(sll, SLL, 0x89) /* type = RS_A SHIFT LEFT SINGLE LOGICAL (32) */ \ 1031 V(sra, SRA, 0x8A) /* type = RS_A SHIFT RIGHT SINGLE (32) */ \ 1032 V(sla, SLA, 0x8B) /* type = RS_A SHIFT LEFT SINGLE (32) */ \ 1033 V(srdl, SRDL, 0x8C) /* type = RS_A SHIFT RIGHT DOUBLE LOGICAL (64) */ \ 1034 V(sldl, SLDL, 0x8D) /* type = RS_A SHIFT LEFT DOUBLE LOGICAL (64) */ \ 1035 V(srda, SRDA, 0x8E) /* type = RS_A SHIFT RIGHT DOUBLE (64) */ \ 1036 V(slda, SLDA, 0x8F) /* type = RS_A SHIFT LEFT DOUBLE (64) */ \ 1037 V(stm, STM, 0x90) /* type = RS_A STORE MULTIPLE (32) */ \ 1038 V(lm, LM, 0x98) /* type = RS_A LOAD MULTIPLE (32) */ \ 1039 V(trace, TRACE, 0x99) /* type = RS_A TRACE (32) */ \ 1040 V(lam, LAM, 0x9A) /* type = RS_A LOAD ACCESS MULTIPLE */ \ 1041 V(stam, STAM, 0x9B) /* type = RS_A STORE ACCESS MULTIPLE */ \ 1042 V(mvcle, MVCLE, 0xA8) /* type = RS_A MOVE LONG EXTENDED */ \ 1043 V(clcle, CLCLE, 0xA9) /* type = RS_A COMPARE LOGICAL LONG EXTENDED */ \ 1044 V(sigp, SIGP, 0xAE) /* type = RS_A SIGNAL PROCESSOR */ \ 1045 V(stctl, STCTL, 0xB6) /* type = RS_A STORE CONTROL (32) */ \ 1046 V(lctl, LCTL, 0xB7) /* type = RS_A LOAD CONTROL (32) */ \ 1047 V(cs, CS, 0xBA) /* type = RS_A COMPARE AND SWAP (32) */ \ 1048 V(cds, CDS, 0xBB) /* type = RS_A COMPARE DOUBLE AND SWAP (32) */ 1049 1050 #define S390_RS_B_OPCODE_LIST(V) \ 1051 V(clm, CLM, 0xBD) /* type = RS_B COMPARE LOGICAL CHAR. UNDER MASK (low) */ \ 1052 V(stcm, STCM, 0xBE) /* type = RS_B STORE CHARACTERS UNDER MASK (low) */ \ 1053 V(icm, ICM, 0xBF) /* type = RS_B INSERT CHARACTERS UNDER MASK (low) */ 1054 1055 #define S390_S_OPCODE_LIST(V) \ 1056 V(lpsw, LPSW, 0x82) /* type = S LOAD PSW */ \ 1057 V(diagnose, DIAGNOSE, 0x83) /* type = S DIAGNOSE */ \ 1058 V(ts, TS, 0x93) /* type = S TEST AND SET */ \ 1059 V(stidp, STIDP, 0xB202) /* type = S STORE CPU ID */ \ 1060 V(sck, SCK, 0xB204) /* type = S SET CLOCK */ \ 1061 V(stck, STCK, 0xB205) /* type = S STORE CLOCK */ \ 1062 V(sckc, SCKC, 0xB206) /* type = S SET CLOCK COMPARATOR */ \ 1063 V(stckc, STCKC, 0xB207) /* type = S STORE CLOCK COMPARATOR */ \ 1064 V(spt, SPT, 0xB208) /* type = S SET CPU TIMER */ \ 1065 V(stpt, STPT, 0xB209) /* type = S STORE CPU TIMER */ \ 1066 V(spka, SPKA, 0xB20A) /* type = S SET PSW KEY FROM ADDRESS */ \ 1067 V(ipk, IPK, 0xB20B) /* type = S INSERT PSW KEY */ \ 1068 V(ptlb, PTLB, 0xB20D) /* type = S PURGE TLB */ \ 1069 V(spx, SPX, 0xB210) /* type = S SET PREFIX */ \ 1070 V(stpx, STPX, 0xB211) /* type = S STORE PREFIX */ \ 1071 V(stap, STAP, 0xB212) /* type = S STORE CPU ADDRESS */ \ 1072 V(pc, PC, 0xB218) /* type = S PROGRAM CALL */ \ 1073 V(sac, SAC, 0xB219) /* type = S SET ADDRESS SPACE CONTROL */ \ 1074 V(cfc, CFC, 0xB21A) /* type = S COMPARE AND FORM CODEWORD */ \ 1075 V(csch, CSCH, 0xB230) /* type = S CLEAR SUBCHANNEL */ \ 1076 V(hsch, HSCH, 0xB231) /* type = S HALT SUBCHANNEL */ \ 1077 V(msch, MSCH, 0xB232) /* type = S MODIFY SUBCHANNEL */ \ 1078 V(ssch, SSCH, 0xB233) /* type = S START SUBCHANNEL */ \ 1079 V(stsch, STSCH, 0xB234) /* type = S STORE SUBCHANNEL */ \ 1080 V(tsch, TSCH, 0xB235) /* type = S TEST SUBCHANNEL */ \ 1081 V(tpi, TPI, 0xB236) /* type = S TEST PENDING INTERRUPTION */ \ 1082 V(sal, SAL, 0xB237) /* type = S SET ADDRESS LIMIT */ \ 1083 V(rsch, RSCH, 0xB238) /* type = S RESUME SUBCHANNEL */ \ 1084 V(stcrw, STCRW, 0xB239) /* type = S STORE CHANNEL REPORT WORD */ \ 1085 V(stcps, STCPS, 0xB23A) /* type = S STORE CHANNEL PATH STATUS */ \ 1086 V(rchp, RCHP, 0xB23B) /* type = S RESET CHANNEL PATH */ \ 1087 V(schm, SCHM, 0xB23C) /* type = S SET CHANNEL MONITOR */ \ 1088 V(xsch, XSCH, 0xB276) /* type = S CANCEL SUBCHANNEL */ \ 1089 V(rp, RP_Z, 0xB277) /* type = S RESUME PROGRAM */ \ 1090 V(stcke, STCKE, 0xB278) /* type = S STORE CLOCK EXTENDED */ \ 1091 V(sacf, SACF, 0xB279) /* type = S SET ADDRESS SPACE CONTROL FAST */ \ 1092 V(stckf, STCKF, 0xB27C) /* type = S STORE CLOCK FAST */ \ 1093 V(stsi, STSI, 0xB27D) /* type = S STORE SYSTEM INFORMATION */ \ 1094 V(srnm, SRNM, 0xB299) /* type = S SET BFP ROUNDING MODE (2 bit) */ \ 1095 V(stfpc, STFPC, 0xB29C) /* type = S STORE FPC */ \ 1096 V(lfpc, LFPC, 0xB29D) /* type = S LOAD FPC */ \ 1097 V(stfle, STFLE, 0xB2B0) /* type = S STORE FACILITY LIST EXTENDED */ \ 1098 V(stfl, STFL, 0xB2B1) /* type = S STORE FACILITY LIST */ \ 1099 V(lpswe, LPSWE, 0xB2B2) /* type = S LOAD PSW EXTENDED */ \ 1100 V(srnmb, SRNMB, 0xB2B8) /* type = S SET BFP ROUNDING MODE (3 bit) */ \ 1101 V(srnmt, SRNMT, 0xB2B9) /* type = S SET DFP ROUNDING MODE */ \ 1102 V(lfas, LFAS, 0xB2BD) /* type = S LOAD FPC AND SIGNAL */ \ 1103 V(tend, TEND, 0xB2F8) /* type = S TRANSACTION END */ \ 1104 V(tabort, TABORT, 0xB2FC) /* type = S TRANSACTION ABORT */ \ 1105 V(trap4, TRAP4, 0xB2FF) /* type = S TRAP */ 1106 1107 #define S390_RX_A_OPCODE_LIST(V) \ 1108 V(la, LA, 0x41) /* type = RX_A LOAD ADDRESS */ \ 1109 V(stc, STC, 0x42) /* type = RX_A STORE CHARACTER */ \ 1110 V(ic_z, IC_z, 0x43) /* type = RX_A INSERT CHARACTER */ \ 1111 V(ex, EX, 0x44) /* type = RX_A EXECUTE */ \ 1112 V(bal, BAL, 0x45) /* type = RX_A BRANCH AND LINK */ \ 1113 V(bct, BCT, 0x46) /* type = RX_A BRANCH ON COUNT (32) */ \ 1114 V(lh, LH, 0x48) /* type = RX_A LOAD HALFWORD (32<-16) */ \ 1115 V(ch, CH, 0x49) /* type = RX_A COMPARE HALFWORD (32<-16) */ \ 1116 V(ah, AH, 0x4A) /* type = RX_A ADD HALFWORD (32<-16) */ \ 1117 V(sh, SH, 0x4B) /* type = RX_A SUBTRACT HALFWORD (32<-16) */ \ 1118 V(mh, MH, 0x4C) /* type = RX_A MULTIPLY HALFWORD (32<-16) */ \ 1119 V(bas, BAS, 0x4D) /* type = RX_A BRANCH AND SAVE */ \ 1120 V(cvd, CVD, 0x4E) /* type = RX_A CONVERT TO DECIMAL (32) */ \ 1121 V(cvb, CVB, 0x4F) /* type = RX_A CONVERT TO BINARY (32) */ \ 1122 V(st, ST, 0x50) /* type = RX_A STORE (32) */ \ 1123 V(lae, LAE, 0x51) /* type = RX_A LOAD ADDRESS EXTENDED */ \ 1124 V(n, N, 0x54) /* type = RX_A AND (32) */ \ 1125 V(cl, CL, 0x55) /* type = RX_A COMPARE LOGICAL (32) */ \ 1126 V(o, O, 0x56) /* type = RX_A OR (32) */ \ 1127 V(x, X, 0x57) /* type = RX_A EXCLUSIVE OR (32) */ \ 1128 V(l, L, 0x58) /* type = RX_A LOAD (32) */ \ 1129 V(c, C, 0x59) /* type = RX_A COMPARE (32) */ \ 1130 V(a, A, 0x5A) /* type = RX_A ADD (32) */ \ 1131 V(s, S, 0x5B) /* type = RX_A SUBTRACT (32) */ \ 1132 V(m, M, 0x5C) /* type = RX_A MULTIPLY (64<-32) */ \ 1133 V(d, D, 0x5D) /* type = RX_A DIVIDE (32<-64) */ \ 1134 V(al_z, AL, 0x5E) /* type = RX_A ADD LOGICAL (32) */ \ 1135 V(sl, SL, 0x5F) /* type = RX_A SUBTRACT LOGICAL (32) */ \ 1136 V(std, STD, 0x60) /* type = RX_A STORE (long) */ \ 1137 V(mxd, MXD, 0x67) /* type = RX_A MULTIPLY (long to extended HFP) */ \ 1138 V(ld, LD, 0x68) /* type = RX_A LOAD (long) */ \ 1139 V(cd, CD, 0x69) /* type = RX_A COMPARE (long HFP) */ \ 1140 V(ad, AD, 0x6A) /* type = RX_A ADD NORMALIZED (long HFP) */ \ 1141 V(sd, SD, 0x6B) /* type = RX_A SUBTRACT NORMALIZED (long HFP) */ \ 1142 V(md, MD, 0x6C) /* type = RX_A MULTIPLY (long HFP) */ \ 1143 V(dd, DD, 0x6D) /* type = RX_A DIVIDE (long HFP) */ \ 1144 V(aw, AW, 0x6E) /* type = RX_A ADD UNNORMALIZED (long HFP) */ \ 1145 V(sw, SW, 0x6F) /* type = RX_A SUBTRACT UNNORMALIZED (long HFP) */ \ 1146 V(ste, STE, 0x70) /* type = RX_A STORE (short) */ \ 1147 V(ms, MS, 0x71) /* type = RX_A MULTIPLY SINGLE (32) */ \ 1148 V(le_z, LE, 0x78) /* type = RX_A LOAD (short) */ \ 1149 V(ce, CE, 0x79) /* type = RX_A COMPARE (short HFP) */ \ 1150 V(ae, AE, 0x7A) /* type = RX_A ADD NORMALIZED (short HFP) */ \ 1151 V(se, SE, 0x7B) /* type = RX_A SUBTRACT NORMALIZED (short HFP) */ \ 1152 V(mde, MDE, 0x7C) /* type = RX_A MULTIPLY (short to long HFP) */ \ 1153 V(de, DE, 0x7D) /* type = RX_A DIVIDE (short HFP) */ \ 1154 V(au, AU, 0x7E) /* type = RX_A ADD UNNORMALIZED (short HFP) */ \ 1155 V(su, SU, 0x7F) /* type = RX_A SUBTRACT UNNORMALIZED (short HFP) */ \ 1156 V(ssm, SSM, 0x80) /* type = RX_A SET SYSTEM MASK */ \ 1157 V(lra, LRA, 0xB1) /* type = RX_A LOAD REAL ADDRESS (32) */ \ 1158 V(sth, STH, 0x40) /* type = RX_A STORE HALFWORD (16) */ 1159 1160 #define S390_RX_B_OPCODE_LIST(V) \ 1161 V(bc, BC, 0x47) /* type = RX_B BRANCH ON CONDITION */ 1162 1163 #define S390_RIE_A_OPCODE_LIST(V) \ 1164 V(cgit, CGIT, 0xEC70) /* type = RIE_A COMPARE IMMEDIATE AND TRAP (64<-16) */ \ 1165 V(clgit, CLGIT, \ 1166 0xEC71) /* type = RIE_A COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) */ \ 1167 V(cit, CIT, 0xEC72) /* type = RIE_A COMPARE IMMEDIATE AND TRAP (32<-16) */ \ 1168 V(clfit, CLFIT, \ 1169 0xEC73) /* type = RIE_A COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) */ 1170 1171 #define S390_RRD_OPCODE_LIST(V) \ 1172 V(maebr, MAEBR, 0xB30E) /* type = RRD MULTIPLY AND ADD (short BFP) */ \ 1173 V(msebr, MSEBR, 0xB30F) /* type = RRD MULTIPLY AND SUBTRACT (short BFP) */ \ 1174 V(madbr, MADBR, 0xB31E) /* type = RRD MULTIPLY AND ADD (long BFP) */ \ 1175 V(msdbr, MSDBR, 0xB31F) /* type = RRD MULTIPLY AND SUBTRACT (long BFP) */ \ 1176 V(maer, MAER, 0xB32E) /* type = RRD MULTIPLY AND ADD (short HFP) */ \ 1177 V(mser, MSER, 0xB32F) /* type = RRD MULTIPLY AND SUBTRACT (short HFP) */ \ 1178 V(maylr, MAYLR, \ 1179 0xB338) /* type = RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) */ \ 1180 V(mylr, MYLR, \ 1181 0xB339) /* type = RRD MULTIPLY UNNORM. (long to ext. low HFP) */ \ 1182 V(mayr, MAYR, \ 1183 0xB33A) /* type = RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) */ \ 1184 V(myr, MYR, \ 1185 0xB33B) /* type = RRD MULTIPLY UNNORMALIZED (long to ext. HFP) */ \ 1186 V(mayhr, MAYHR, \ 1187 0xB33C) /* type = RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) */ \ 1188 V(myhr, MYHR, \ 1189 0xB33D) /* type = RRD MULTIPLY UNNORM. (long to ext. high HFP) */ \ 1190 V(madr, MADR, 0xB33E) /* type = RRD MULTIPLY AND ADD (long HFP) */ \ 1191 V(msdr, MSDR, 0xB33F) /* type = RRD MULTIPLY AND SUBTRACT (long HFP) */ 1192 1193 #define S390_RIE_B_OPCODE_LIST(V) \ 1194 V(cgrj, CGRJ, 0xEC64) /* type = RIE_B COMPARE AND BRANCH RELATIVE (64) */ \ 1195 V(clgrj, CLGRJ, \ 1196 0xEC65) /* type = RIE_B COMPARE LOGICAL AND BRANCH RELATIVE (64) */ \ 1197 V(crj, CRJ, 0xEC76) /* type = RIE_B COMPARE AND BRANCH RELATIVE (32) */ \ 1198 V(clrj, CLRJ, \ 1199 0xEC77) /* type = RIE_B COMPARE LOGICAL AND BRANCH RELATIVE (32) */ 1200 1201 #define S390_RRE_OPCODE_LIST(V) \ 1202 V(ipm, IPM, 0xB222) /* type = RRE INSERT PROGRAM MASK */ \ 1203 V(ivsk, IVSK, 0xB223) /* type = RRE INSERT VIRTUAL STORAGE KEY */ \ 1204 V(iac, IAC, 0xB224) /* type = RRE INSERT ADDRESS SPACE CONTROL */ \ 1205 V(ssar, SSAR, 0xB225) /* type = RRE SET SECONDARY ASN */ \ 1206 V(epar, EPAR, 0xB226) /* type = RRE EXTRACT PRIMARY ASN */ \ 1207 V(esar, ESAR, 0xB227) /* type = RRE EXTRACT SECONDARY ASN */ \ 1208 V(pt, PT, 0xB228) /* type = RRE PROGRAM TRANSFER */ \ 1209 V(iske, ISKE, 0xB229) /* type = RRE INSERT STORAGE KEY EXTENDED */ \ 1210 V(rrbe, RRBE, 0xB22A) /* type = RRE RESET REFERENCE BIT EXTENDED */ \ 1211 V(tb, TB, 0xB22C) /* type = RRE TEST BLOCK */ \ 1212 V(dxr, DXR, 0xB22D) /* type = RRE DIVIDE (extended HFP) */ \ 1213 V(pgin, PGIN, 0xB22E) /* type = RRE PAGE IN */ \ 1214 V(pgout, PGOUT, 0xB22F) /* type = RRE PAGE OUT */ \ 1215 V(bakr, BAKR, 0xB240) /* type = RRE BRANCH AND STACK */ \ 1216 V(cksm, CKSM, 0xB241) /* type = RRE CHECKSUM */ \ 1217 V(sqdr, SQDR, 0xB244) /* type = RRE SQUARE ROOT (long HFP) */ \ 1218 V(sqer, SQER, 0xB245) /* type = RRE SQUARE ROOT (short HFP) */ \ 1219 V(stura, STURA, 0xB246) /* type = RRE STORE USING REAL ADDRESS (32) */ \ 1220 V(msta, MSTA, 0xB247) /* type = RRE MODIFY STACKED STATE */ \ 1221 V(palb, PALB, 0xB248) /* type = RRE PURGE ALB */ \ 1222 V(ereg, EREG, 0xB249) /* type = RRE EXTRACT STACKED REGISTERS (32) */ \ 1223 V(esta, ESTA, 0xB24A) /* type = RRE EXTRACT STACKED STATE */ \ 1224 V(lura, LURA, 0xB24B) /* type = RRE LOAD USING REAL ADDRESS (32) */ \ 1225 V(tar, TAR, 0xB24C) /* type = RRE TEST ACCESS */ \ 1226 V(cpya, CPYA, 0xB24D) /* type = RRE COPY ACCESS */ \ 1227 V(sar, SAR, 0xB24E) /* type = RRE SET ACCESS */ \ 1228 V(ear, EAR, 0xB24F) /* type = RRE EXTRACT ACCESS */ \ 1229 V(csp, CSP, 0xB250) /* type = RRE COMPARE AND SWAP AND PURGE (32) */ \ 1230 V(msr, MSR, 0xB252) /* type = RRE MULTIPLY SINGLE (32) */ \ 1231 V(mvpg, MVPG, 0xB254) /* type = RRE MOVE PAGE */ \ 1232 V(mvst, MVST, 0xB255) /* type = RRE MOVE STRING */ \ 1233 V(cuse, CUSE, 0xB257) /* type = RRE COMPARE UNTIL SUBSTRING EQUAL */ \ 1234 V(bsg, BSG, 0xB258) /* type = RRE BRANCH IN SUBSPACE GROUP */ \ 1235 V(bsa, BSA, 0xB25A) /* type = RRE BRANCH AND SET AUTHORITY */ \ 1236 V(clst, CLST, 0xB25D) /* type = RRE COMPARE LOGICAL STRING */ \ 1237 V(srst, SRST, 0xB25E) /* type = RRE SEARCH STRING */ \ 1238 V(cmpsc, CMPSC, 0xB263) /* type = RRE COMPRESSION CALL */ \ 1239 V(tre, TRE, 0xB2A5) /* type = RRE TRANSLATE EXTENDED */ \ 1240 V(etnd, ETND, 0xB2EC) /* type = RRE EXTRACT TRANSACTION NESTING DEPTH */ \ 1241 V(lpebr, LPEBR, 0xB300) /* type = RRE LOAD POSITIVE (short BFP) */ \ 1242 V(lnebr, LNEBR, 0xB301) /* type = RRE LOAD NEGATIVE (short BFP) */ \ 1243 V(ltebr, LTEBR, 0xB302) /* type = RRE LOAD AND TEST (short BFP) */ \ 1244 V(lcebr, LCEBR, 0xB303) /* type = RRE LOAD COMPLEMENT (short BFP) */ \ 1245 V(ldebr, LDEBR, \ 1246 0xB304) /* type = RRE LOAD LENGTHENED (short to long BFP) */ \ 1247 V(lxdbr, LXDBR, \ 1248 0xB305) /* type = RRE LOAD LENGTHENED (long to extended BFP) */ \ 1249 V(lxebr, LXEBR, \ 1250 0xB306) /* type = RRE LOAD LENGTHENED (short to extended BFP) */ \ 1251 V(mxdbr, MXDBR, 0xB307) /* type = RRE MULTIPLY (long to extended BFP) */ \ 1252 V(kebr, KEBR, 0xB308) /* type = RRE COMPARE AND SIGNAL (short BFP) */ \ 1253 V(cebr, CEBR, 0xB309) /* type = RRE COMPARE (short BFP) */ \ 1254 V(aebr, AEBR, 0xB30A) /* type = RRE ADD (short BFP) */ \ 1255 V(sebr, SEBR, 0xB30B) /* type = RRE SUBTRACT (short BFP) */ \ 1256 V(mdebr, MDEBR, 0xB30C) /* type = RRE MULTIPLY (short to long BFP) */ \ 1257 V(debr, DEBR, 0xB30D) /* type = RRE DIVIDE (short BFP) */ \ 1258 V(lpdbr, LPDBR, 0xB310) /* type = RRE LOAD POSITIVE (long BFP) */ \ 1259 V(lndbr, LNDBR, 0xB311) /* type = RRE LOAD NEGATIVE (long BFP) */ \ 1260 V(ltdbr, LTDBR, 0xB312) /* type = RRE LOAD AND TEST (long BFP) */ \ 1261 V(lcdbr, LCDBR, 0xB313) /* type = RRE LOAD COMPLEMENT (long BFP) */ \ 1262 V(sqebr, SQEBR, 0xB314) /* type = RRE SQUARE ROOT (short BFP) */ \ 1263 V(sqdbr, SQDBR, 0xB315) /* type = RRE SQUARE ROOT (long BFP) */ \ 1264 V(sqxbr, SQXBR, 0xB316) /* type = RRE SQUARE ROOT (extended BFP) */ \ 1265 V(meebr, MEEBR, 0xB317) /* type = RRE MULTIPLY (short BFP) */ \ 1266 V(kdbr, KDBR, 0xB318) /* type = RRE COMPARE AND SIGNAL (long BFP) */ \ 1267 V(cdbr, CDBR, 0xB319) /* type = RRE COMPARE (long BFP) */ \ 1268 V(adbr, ADBR, 0xB31A) /* type = RRE ADD (long BFP) */ \ 1269 V(sdbr, SDBR, 0xB31B) /* type = RRE SUBTRACT (long BFP) */ \ 1270 V(mdbr, MDBR, 0xB31C) /* type = RRE MULTIPLY (long BFP) */ \ 1271 V(ddbr, DDBR, 0xB31D) /* type = RRE DIVIDE (long BFP) */ \ 1272 V(lder, LDER, 0xB324) /* type = RRE LOAD LENGTHENED (short to long HFP) */ \ 1273 V(lxdr, LXDR, \ 1274 0xB325) /* type = RRE LOAD LENGTHENED (long to extended HFP) */ \ 1275 V(lxer, LXER, \ 1276 0xB326) /* type = RRE LOAD LENGTHENED (short to extended HFP) */ \ 1277 V(sqxr, SQXR, 0xB336) /* type = RRE SQUARE ROOT (extended HFP) */ \ 1278 V(meer, MEER, 0xB337) /* type = RRE MULTIPLY (short HFP) */ \ 1279 V(lpxbr, LPXBR, 0xB340) /* type = RRE LOAD POSITIVE (extended BFP) */ \ 1280 V(lnxbr, LNXBR, 0xB341) /* type = RRE LOAD NEGATIVE (extended BFP) */ \ 1281 V(ltxbr, LTXBR, 0xB342) /* type = RRE LOAD AND TEST (extended BFP) */ \ 1282 V(lcxbr, LCXBR, 0xB343) /* type = RRE LOAD COMPLEMENT (extended BFP) */ \ 1283 V(kxbr, KXBR, 0xB348) /* type = RRE COMPARE AND SIGNAL (extended BFP) */ \ 1284 V(cxbr, CXBR, 0xB349) /* type = RRE COMPARE (extended BFP) */ \ 1285 V(axbr, AXBR, 0xB34A) /* type = RRE ADD (extended BFP) */ \ 1286 V(sxbr, SXBR, 0xB34B) /* type = RRE SUBTRACT (extended BFP) */ \ 1287 V(mxbr, MXBR, 0xB34C) /* type = RRE MULTIPLY (extended BFP) */ \ 1288 V(dxbr, DXBR, 0xB34D) /* type = RRE DIVIDE (extended BFP) */ \ 1289 V(thder, THDER, \ 1290 0xB358) /* type = RRE CONVERT BFP TO HFP (short to long) */ \ 1291 V(thdr, THDR, 0xB359) /* type = RRE CONVERT BFP TO HFP (long) */ \ 1292 V(lpxr, LPXR, 0xB360) /* type = RRE LOAD POSITIVE (extended HFP) */ \ 1293 V(lnxr, LNXR, 0xB361) /* type = RRE LOAD NEGATIVE (extended HFP) */ \ 1294 V(ltxr, LTXR, 0xB362) /* type = RRE LOAD AND TEST (extended HFP) */ \ 1295 V(lcxr, LCXR, 0xB363) /* type = RRE LOAD COMPLEMENT (extended HFP) */ \ 1296 V(lxr, LXR, 0xB365) /* type = RRE LOAD (extended) */ \ 1297 V(lexr, LEXR, \ 1298 0xB366) /* type = RRE LOAD ROUNDED (extended to short HFP) */ \ 1299 V(fixr, FIXR, 0xB367) /* type = RRE LOAD FP INTEGER (extended HFP) */ \ 1300 V(cxr, CXR, 0xB369) /* type = RRE COMPARE (extended HFP) */ \ 1301 V(lpdfr, LPDFR, 0xB370) /* type = RRE LOAD POSITIVE (long) */ \ 1302 V(lndfr, LNDFR, 0xB371) /* type = RRE LOAD NEGATIVE (long) */ \ 1303 V(lcdfr, LCDFR, 0xB373) /* type = RRE LOAD COMPLEMENT (long) */ \ 1304 V(lzer, LZER, 0xB374) /* type = RRE LOAD ZERO (short) */ \ 1305 V(lzdr, LZDR, 0xB375) /* type = RRE LOAD ZERO (long) */ \ 1306 V(lzxr, LZXR, 0xB376) /* type = RRE LOAD ZERO (extended) */ \ 1307 V(fier, FIER, 0xB377) /* type = RRE LOAD FP INTEGER (short HFP) */ \ 1308 V(fidr, FIDR, 0xB37F) /* type = RRE LOAD FP INTEGER (long HFP) */ \ 1309 V(sfpc, SFPC, 0xB384) /* type = RRE SET FPC */ \ 1310 V(sfasr, SFASR, 0xB385) /* type = RRE SET FPC AND SIGNAL */ \ 1311 V(efpc, EFPC, 0xB38C) /* type = RRE EXTRACT FPC */ \ 1312 V(cefr, CEFR, \ 1313 0xB3B4) /* type = RRE CONVERT FROM FIXED (32 to short HFP) */ \ 1314 V(cdfr, CDFR, 0xB3B5) /* type = RRE CONVERT FROM FIXED (32 to long HFP) */ \ 1315 V(cxfr, CXFR, \ 1316 0xB3B6) /* type = RRE CONVERT FROM FIXED (32 to extended HFP) */ \ 1317 V(ldgr, LDGR, 0xB3C1) /* type = RRE LOAD FPR FROM GR (64 to long) */ \ 1318 V(cegr, CEGR, \ 1319 0xB3C4) /* type = RRE CONVERT FROM FIXED (64 to short HFP) */ \ 1320 V(cdgr, CDGR, 0xB3C5) /* type = RRE CONVERT FROM FIXED (64 to long HFP) */ \ 1321 V(cxgr, CXGR, \ 1322 0xB3C6) /* type = RRE CONVERT FROM FIXED (64 to extended HFP) */ \ 1323 V(lgdr, LGDR, 0xB3CD) /* type = RRE LOAD GR FROM FPR (long to 64) */ \ 1324 V(ltdtr, LTDTR, 0xB3D6) /* type = RRE LOAD AND TEST (long DFP) */ \ 1325 V(ltxtr, LTXTR, 0xB3DE) /* type = RRE LOAD AND TEST (extended DFP) */ \ 1326 V(kdtr, KDTR, 0xB3E0) /* type = RRE COMPARE AND SIGNAL (long DFP) */ \ 1327 V(cudtr, CUDTR, 0xB3E2) /* type = RRE CONVERT TO UNSIGNED PACKED (long */ \ 1328 /* DFP to 64) CUDTR */ \ 1329 V(cdtr, CDTR, 0xB3E4) /* type = RRE COMPARE (long DFP) */ \ 1330 V(eedtr, EEDTR, \ 1331 0xB3E5) /* type = RRE EXTRACT BIASED EXPONENT (long DFP to 64) */ \ 1332 V(esdtr, ESDTR, \ 1333 0xB3E7) /* type = RRE EXTRACT SIGNIFICANCE (long DFP to 64) */ \ 1334 V(kxtr, KXTR, 0xB3E8) /* type = RRE COMPARE AND SIGNAL (extended DFP) */ \ 1335 V(cuxtr, CUXTR, \ 1336 0xB3EA) /* type = RRE CONVERT TO UNSIGNED PACKED (extended DFP */ \ 1337 /* CUXTR to 128) */ \ 1338 V(cxtr, CXTR, 0xB3EC) /* type = RRE COMPARE (extended DFP) */ \ 1339 V(eextr, EEXTR, \ 1340 0xB3ED) /* type = RRE EXTRACT BIASED EXPONENT (extended DFP to 64) */ \ 1341 V(esxtr, ESXTR, \ 1342 0xB3EF) /* type = RRE EXTRACT SIGNIFICANCE (extended DFP to 64) */ \ 1343 V(cdutr, CDUTR, \ 1344 0xB3F2) /* type = RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) */ \ 1345 V(cdstr, CDSTR, \ 1346 0xB3F3) /* type = RRE CONVERT FROM SIGNED PACKED (64 to long DFP) */ \ 1347 V(cedtr, CEDTR, \ 1348 0xB3F4) /* type = RRE COMPARE BIASED EXPONENT (long DFP) */ \ 1349 V(cxutr, CXUTR, \ 1350 0xB3FA) /* type = RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) */ \ 1351 V(cxstr, CXSTR, 0xB3FB) /* type = RRE CONVERT FROM SIGNED PACKED (128 to*/ \ 1352 /* extended DFP) */ \ 1353 V(cextr, CEXTR, \ 1354 0xB3FC) /* type = RRE COMPARE BIASED EXPONENT (extended DFP) */ \ 1355 V(lpgr, LPGR, 0xB900) /* type = RRE LOAD POSITIVE (64) */ \ 1356 V(lngr, LNGR, 0xB901) /* type = RRE LOAD NEGATIVE (64) */ \ 1357 V(ltgr, LTGR, 0xB902) /* type = RRE LOAD AND TEST (64) */ \ 1358 V(lcgr, LCGR, 0xB903) /* type = RRE LOAD COMPLEMENT (64) */ \ 1359 V(lgr, LGR, 0xB904) /* type = RRE LOAD (64) */ \ 1360 V(lurag, LURAG, 0xB905) /* type = RRE LOAD USING REAL ADDRESS (64) */ \ 1361 V(lgbr, LGBR, 0xB906) /* type = RRE LOAD BYTE (64<-8) */ \ 1362 V(lghr, LGHR, 0xB907) /* type = RRE LOAD HALFWORD (64<-16) */ \ 1363 V(agr, AGR, 0xB908) /* type = RRE ADD (64) */ \ 1364 V(sgr, SGR, 0xB909) /* type = RRE SUBTRACT (64) */ \ 1365 V(algr, ALGR, 0xB90A) /* type = RRE ADD LOGICAL (64) */ \ 1366 V(slgr, SLGR, 0xB90B) /* type = RRE SUBTRACT LOGICAL (64) */ \ 1367 V(msgr, MSGR, 0xB90C) /* type = RRE MULTIPLY SINGLE (64) */ \ 1368 V(dsgr, DSGR, 0xB90D) /* type = RRE DIVIDE SINGLE (64) */ \ 1369 V(eregg, EREGG, 0xB90E) /* type = RRE EXTRACT STACKED REGISTERS (64) */ \ 1370 V(lrvgr, LRVGR, 0xB90F) /* type = RRE LOAD REVERSED (64) */ \ 1371 V(lpgfr, LPGFR, 0xB910) /* type = RRE LOAD POSITIVE (64<-32) */ \ 1372 V(lngfr, LNGFR, 0xB911) /* type = RRE LOAD NEGATIVE (64<-32) */ \ 1373 V(ltgfr, LTGFR, 0xB912) /* type = RRE LOAD AND TEST (64<-32) */ \ 1374 V(lcgfr, LCGFR, 0xB913) /* type = RRE LOAD COMPLEMENT (64<-32) */ \ 1375 V(lgfr, LGFR, 0xB914) /* type = RRE LOAD (64<-32) */ \ 1376 V(llgfr, LLGFR, 0xB916) /* type = RRE LOAD LOGICAL (64<-32) */ \ 1377 V(llgtr, LLGTR, \ 1378 0xB917) /* type = RRE LOAD LOGICAL THIRTY ONE BITS (64<-31) */ \ 1379 V(agfr, AGFR, 0xB918) /* type = RRE ADD (64<-32) */ \ 1380 V(sgfr, SGFR, 0xB919) /* type = RRE SUBTRACT (64<-32) */ \ 1381 V(algfr, ALGFR, 0xB91A) /* type = RRE ADD LOGICAL (64<-32) */ \ 1382 V(slgfr, SLGFR, 0xB91B) /* type = RRE SUBTRACT LOGICAL (64<-32) */ \ 1383 V(msgfr, MSGFR, 0xB91C) /* type = RRE MULTIPLY SINGLE (64<-32) */ \ 1384 V(dsgfr, DSGFR, 0xB91D) /* type = RRE DIVIDE SINGLE (64<-32) */ \ 1385 V(kmac, KMAC, 0xB91E) /* type = RRE COMPUTE MESSAGE AUTHENTICATION CODE */ \ 1386 V(lrvr, LRVR, 0xB91F) /* type = RRE LOAD REVERSED (32) */ \ 1387 V(cgr, CGR, 0xB920) /* type = RRE COMPARE (64) */ \ 1388 V(clgr, CLGR, 0xB921) /* type = RRE COMPARE LOGICAL (64) */ \ 1389 V(sturg, STURG, 0xB925) /* type = RRE STORE USING REAL ADDRESS (64) */ \ 1390 V(lbr, LBR, 0xB926) /* type = RRE LOAD BYTE (32<-8) */ \ 1391 V(lhr, LHR, 0xB927) /* type = RRE LOAD HALFWORD (32<-16) */ \ 1392 V(pckmo, PCKMO, \ 1393 0xB928) /* type = RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS */ \ 1394 V(kmf, KMF, 0xB92A) /* type = RRE CIPHER MESSAGE WITH CIPHER FEEDBACK */ \ 1395 V(kmo, KMO, 0xB92B) /* type = RRE CIPHER MESSAGE WITH OUTPUT FEEDBACK */ \ 1396 V(pcc, PCC, 0xB92C) /* type = RRE PERFORM CRYPTOGRAPHIC COMPUTATION */ \ 1397 V(km, KM, 0xB92E) /* type = RRE CIPHER MESSAGE */ \ 1398 V(kmc, KMC, 0xB92F) /* type = RRE CIPHER MESSAGE WITH CHAINING */ \ 1399 V(cgfr, CGFR, 0xB930) /* type = RRE COMPARE (64<-32) */ \ 1400 V(clgfr, CLGFR, 0xB931) /* type = RRE COMPARE LOGICAL (64<-32) */ \ 1401 V(ppno, PPNO, \ 1402 0xB93C) /* type = RRE PERFORM PSEUDORANDOM NUMBER OPERATION */ \ 1403 V(kimd, KIMD, 0xB93E) /* type = RRE COMPUTE INTERMEDIATE MESSAGE DIGEST */ \ 1404 V(klmd, KLMD, 0xB93F) /* type = RRE COMPUTE LAST MESSAGE DIGEST */ \ 1405 V(bctgr, BCTGR, 0xB946) /* type = RRE BRANCH ON COUNT (64) */ \ 1406 V(cdftr, CDFTR, \ 1407 0xB951) /* type = RRE CONVERT FROM FIXED (32 to long DFP) */ \ 1408 V(cxftr, CXFTR, \ 1409 0xB959) /* type = RRE CONVERT FROM FIXED (32 to extended DFP) */ \ 1410 V(ngr, NGR, 0xB980) /* type = RRE AND (64) */ \ 1411 V(ogr, OGR, 0xB981) /* type = RRE OR (64) */ \ 1412 V(xgr, XGR, 0xB982) /* type = RRE EXCLUSIVE OR (64) */ \ 1413 V(flogr, FLOGR, 0xB983) /* type = RRE FIND LEFTMOST ONE */ \ 1414 V(llgcr, LLGCR, 0xB984) /* type = RRE LOAD LOGICAL CHARACTER (64<-8) */ \ 1415 V(llghr, LLGHR, 0xB985) /* type = RRE LOAD LOGICAL HALFWORD (64<-16) */ \ 1416 V(mlgr, MLGR, 0xB986) /* type = RRE MULTIPLY LOGICAL (128<-64) */ \ 1417 V(dlgr, DLGR, 0xB987) /* type = RRE DIVIDE LOGICAL (64<-128) */ \ 1418 V(alcgr, ALCGR, 0xB988) /* type = RRE ADD LOGICAL WITH CARRY (64) */ \ 1419 V(slbgr, SLBGR, 0xB989) /* type = RRE SUBTRACT LOGICAL WITH BORROW (64) */ \ 1420 V(cspg, CSPG, 0xB98A) /* type = RRE COMPARE AND SWAP AND PURGE (64) */ \ 1421 V(epsw, EPSW, 0xB98D) /* type = RRE EXTRACT PSW */ \ 1422 V(llcr, LLCR, 0xB994) /* type = RRE LOAD LOGICAL CHARACTER (32<-8) */ \ 1423 V(llhr, LLHR, 0xB995) /* type = RRE LOAD LOGICAL HALFWORD (32<-16) */ \ 1424 V(mlr, MLR, 0xB996) /* type = RRE MULTIPLY LOGICAL (64<-32) */ \ 1425 V(dlr, DLR, 0xB997) /* type = RRE DIVIDE LOGICAL (32<-64) */ \ 1426 V(alcr, ALCR, 0xB998) /* type = RRE ADD LOGICAL WITH CARRY (32) */ \ 1427 V(slbr, SLBR, 0xB999) /* type = RRE SUBTRACT LOGICAL WITH BORROW (32) */ \ 1428 V(epair, EPAIR, 0xB99A) /* type = RRE EXTRACT PRIMARY ASN AND INSTANCE */ \ 1429 V(esair, ESAIR, \ 1430 0xB99B) /* type = RRE EXTRACT SECONDARY ASN AND INSTANCE */ \ 1431 V(esea, ESEA, 0xB99D) /* type = RRE EXTRACT AND SET EXTENDED AUTHORITY */ \ 1432 V(pti, PTI, 0xB99E) /* type = RRE PROGRAM TRANSFER WITH INSTANCE */ \ 1433 V(ssair, SSAIR, 0xB99F) /* type = RRE SET SECONDARY ASN WITH INSTANCE */ \ 1434 V(ptf, PTF, 0xB9A2) /* type = RRE PERFORM TOPOLOGY FUNCTION */ \ 1435 V(rrbm, RRBM, 0xB9AE) /* type = RRE RESET REFERENCE BITS MULTIPLE */ \ 1436 V(pfmf, PFMF, 0xB9AF) /* type = RRE PERFORM FRAME MANAGEMENT FUNCTION */ \ 1437 V(cu41, CU41, 0xB9B2) /* type = RRE CONVERT UTF-32 TO UTF-8 */ \ 1438 V(cu42, CU42, 0xB9B3) /* type = RRE CONVERT UTF-32 TO UTF-16 */ \ 1439 V(srstu, SRSTU, 0xB9BE) /* type = RRE SEARCH STRING UNICODE */ \ 1440 V(chhr, CHHR, 0xB9CD) /* type = RRE COMPARE HIGH (32) */ \ 1441 V(clhhr, CLHHR, 0xB9CF) /* type = RRE COMPARE LOGICAL HIGH (32) */ \ 1442 V(chlr, CHLR, 0xB9DD) /* type = RRE COMPARE HIGH (32) */ \ 1443 V(clhlr, CLHLR, 0xB9DF) /* type = RRE COMPARE LOGICAL HIGH (32) */ \ 1444 V(popcnt, POPCNT_Z, 0xB9E1) /* type = RRE POPULATION COUNT */ 1445 1446 #define S390_RIE_C_OPCODE_LIST(V) \ 1447 V(cgij, CGIJ, \ 1448 0xEC7C) /* type = RIE_C COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) */ \ 1449 V(clgij, CLGIJ, \ 1450 0xEC7D) /* type = RIE_C COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE */ \ 1451 /* (64<-8) */ \ 1452 V(cij, CIJ, \ 1453 0xEC7E) /* type = RIE_C COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) */ \ 1454 V(clij, CLIJ, 0xEC7F) /* type = RIE_C COMPARE LOGICAL IMMEDIATE AND */ \ 1455 /* BRANCH RELATIVE (32<-8) */ 1456 1457 #define S390_RIE_D_OPCODE_LIST(V) \ 1458 V(ahik, AHIK, 0xECD8) /* type = RIE_D ADD IMMEDIATE (32<-16) */ \ 1459 V(aghik, AGHIK, 0xECD9) /* type = RIE_D ADD IMMEDIATE (64<-16) */ \ 1460 V(alhsik, ALHSIK, \ 1461 0xECDA) /* type = RIE_D ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) */ \ 1462 V(alghsik, ALGHSIK, \ 1463 0xECDB) /* type = RIE_D ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) */ 1464 1465 #define S390_VRV_OPCODE_LIST(V) \ 1466 V(vgeg, VGEG, 0xE712) /* type = VRV VECTOR GATHER ELEMENT (64) */ \ 1467 V(vgef, VGEF, 0xE713) /* type = VRV VECTOR GATHER ELEMENT (32) */ \ 1468 V(vsceg, VSCEG, 0xE71A) /* type = VRV VECTOR SCATTER ELEMENT (64) */ \ 1469 V(vscef, VSCEF, 0xE71B) /* type = VRV VECTOR SCATTER ELEMENT (32) */ 1470 1471 #define S390_RIE_E_OPCODE_LIST(V) \ 1472 V(brxhg, BRXHG, \ 1473 0xEC44) /* type = RIE_E BRANCH RELATIVE ON INDEX HIGH (64) */ \ 1474 V(brxlg, BRXLG, \ 1475 0xEC45) /* type = RIE_E BRANCH RELATIVE ON INDEX LOW OR EQ. (64) */ 1476 1477 #define S390_RR_OPCODE_LIST(V) \ 1478 V(awr, AWR, 0x2E) /* type = RR ADD UNNORMALIZED (long HFP) */ \ 1479 V(spm, SPM, 0x04) /* type = RR SET PROGRAM MASK */ \ 1480 V(balr, BALR, 0x05) /* type = RR BRANCH AND LINK */ \ 1481 V(bctr, BCTR, 0x06) /* type = RR BRANCH ON COUNT (32) */ \ 1482 V(bcr, BCR, 0x07) /* type = RR BRANCH ON CONDITION */ \ 1483 V(bsm, BSM, 0x0B) /* type = RR BRANCH AND SET MODE */ \ 1484 V(bassm, BASSM, 0x0C) /* type = RR BRANCH AND SAVE AND SET MODE */ \ 1485 V(basr, BASR, 0x0D) /* type = RR BRANCH AND SAVE */ \ 1486 V(mvcl, MVCL, 0x0E) /* type = RR MOVE LONG */ \ 1487 V(clcl, CLCL, 0x0F) /* type = RR COMPARE LOGICAL LONG */ \ 1488 V(lpr, LPR, 0x10) /* type = RR LOAD POSITIVE (32) */ \ 1489 V(lnr, LNR, 0x11) /* type = RR LOAD NEGATIVE (32) */ \ 1490 V(ltr, LTR, 0x12) /* type = RR LOAD AND TEST (32) */ \ 1491 V(lcr, LCR, 0x13) /* type = RR LOAD COMPLEMENT (32) */ \ 1492 V(nr, NR, 0x14) /* type = RR AND (32) */ \ 1493 V(clr, CLR, 0x15) /* type = RR COMPARE LOGICAL (32) */ \ 1494 V(or_z, OR, 0x16) /* type = RR OR (32) */ \ 1495 V(xr, XR, 0x17) /* type = RR EXCLUSIVE OR (32) */ \ 1496 V(lr, LR, 0x18) /* type = RR LOAD (32) */ \ 1497 V(cr_z, CR, 0x19) /* type = RR COMPARE (32) */ \ 1498 V(ar, AR, 0x1A) /* type = RR ADD (32) */ \ 1499 V(sr, SR, 0x1B) /* type = RR SUBTRACT (32) */ \ 1500 V(mr_z, MR, 0x1C) /* type = RR MULTIPLY (64<-32) */ \ 1501 V(dr, DR, 0x1D) /* type = RR DIVIDE (32<-64) */ \ 1502 V(alr, ALR, 0x1E) /* type = RR ADD LOGICAL (32) */ \ 1503 V(slr, SLR, 0x1F) /* type = RR SUBTRACT LOGICAL (32) */ \ 1504 V(lpdr, LPDR, 0x20) /* type = RR LOAD POSITIVE (long HFP) */ \ 1505 V(lndr, LNDR, 0x21) /* type = RR LOAD NEGATIVE (long HFP) */ \ 1506 V(ltdr, LTDR, 0x22) /* type = RR LOAD AND TEST (long HFP) */ \ 1507 V(lcdr, LCDR, 0x23) /* type = RR LOAD COMPLEMENT (long HFP) */ \ 1508 V(hdr, HDR, 0x24) /* type = RR HALVE (long HFP) */ \ 1509 V(ldxr, LDXR, 0x25) /* type = RR LOAD ROUNDED (extended to long HFP) */ \ 1510 V(mxr, MXR, 0x26) /* type = RR MULTIPLY (extended HFP) */ \ 1511 V(mxdr, MXDR, 0x27) /* type = RR MULTIPLY (long to extended HFP) */ \ 1512 V(ldr, LDR, 0x28) /* type = RR LOAD (long) */ \ 1513 V(cdr, CDR, 0x29) /* type = RR COMPARE (long HFP) */ \ 1514 V(adr, ADR, 0x2A) /* type = RR ADD NORMALIZED (long HFP) */ \ 1515 V(sdr, SDR, 0x2B) /* type = RR SUBTRACT NORMALIZED (long HFP) */ \ 1516 V(mdr, MDR, 0x2C) /* type = RR MULTIPLY (long HFP) */ \ 1517 V(ddr, DDR, 0x2D) /* type = RR DIVIDE (long HFP) */ \ 1518 V(swr, SWR, 0x2F) /* type = RR SUBTRACT UNNORMALIZED (long HFP) */ \ 1519 V(lper, LPER, 0x30) /* type = RR LOAD POSITIVE (short HFP) */ \ 1520 V(lner, LNER, 0x31) /* type = RR LOAD NEGATIVE (short HFP) */ \ 1521 V(lter, LTER, 0x32) /* type = RR LOAD AND TEST (short HFP) */ \ 1522 V(lcer, LCER, 0x33) /* type = RR LOAD COMPLEMENT (short HFP) */ \ 1523 V(her_z, HER_Z, 0x34) /* type = RR HALVE (short HFP) */ \ 1524 V(ledr, LEDR, 0x35) /* type = RR LOAD ROUNDED (long to short HFP) */ \ 1525 V(axr, AXR, 0x36) /* type = RR ADD NORMALIZED (extended HFP) */ \ 1526 V(sxr, SXR, 0x37) /* type = RR SUBTRACT NORMALIZED (extended HFP) */ \ 1527 V(ler, LER, 0x38) /* type = RR LOAD (short) */ \ 1528 V(cer, CER, 0x39) /* type = RR COMPARE (short HFP) */ \ 1529 V(aer, AER, 0x3A) /* type = RR ADD NORMALIZED (short HFP) */ \ 1530 V(ser, SER, 0x3B) /* type = RR SUBTRACT NORMALIZED (short HFP) */ \ 1531 V(mder, MDER, 0x3C) /* type = RR MULTIPLY (short to long HFP) */ \ 1532 V(der, DER, 0x3D) /* type = RR DIVIDE (short HFP) */ \ 1533 V(aur, AUR, 0x3E) /* type = RR ADD UNNORMALIZED (short HFP) */ \ 1534 V(sur, SUR, 0x3F) /* type = RR SUBTRACT UNNORMALIZED (short HFP) */ 1535 1536 #define S390_RIE_F_OPCODE_LIST(V) \ 1537 V(risblg, RISBLG, \ 1538 0xEC51) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS LOW (64) */ \ 1539 V(rnsbg, RNSBG, \ 1540 0xEC54) /* type = RIE_F ROTATE THEN AND SELECTED BITS (64) */ \ 1541 V(risbg, RISBG, \ 1542 0xEC55) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS (64) */ \ 1543 V(rosbg, ROSBG, 0xEC56) /* type = RIE_F ROTATE THEN OR SELECTED BITS (64) */ \ 1544 V(rxsbg, RXSBG, \ 1545 0xEC57) /* type = RIE_F ROTATE THEN EXCLUSIVE OR SELECT. BITS (64) */ \ 1546 V(risbgn, RISBGN, \ 1547 0xEC59) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS (64) */ \ 1548 V(risbhg, RISBHG, \ 1549 0xEC5D) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS HIGH (64) */ 1550 1551 #define S390_VRX_OPCODE_LIST(V) \ 1552 V(vleb, VLEB, 0xE700) /* type = VRX VECTOR LOAD ELEMENT (8) */ \ 1553 V(vleh, VLEH, 0xE701) /* type = VRX VECTOR LOAD ELEMENT (16) */ \ 1554 V(vleg, VLEG, 0xE702) /* type = VRX VECTOR LOAD ELEMENT (64) */ \ 1555 V(vlef, VLEF, 0xE703) /* type = VRX VECTOR LOAD ELEMENT (32) */ \ 1556 V(vllez, VLLEZ, \ 1557 0xE704) /* type = VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO */ \ 1558 V(vlrep, VLREP, 0xE705) /* type = VRX VECTOR LOAD AND REPLICATE */ \ 1559 V(vl, VL, 0xE706) /* type = VRX VECTOR LOAD */ \ 1560 V(vlbb, VLBB, 0xE707) /* type = VRX VECTOR LOAD TO BLOCK BOUNDARY */ \ 1561 V(vsteb, VSTEB, 0xE708) /* type = VRX VECTOR STORE ELEMENT (8) */ \ 1562 V(vsteh, VSTEH, 0xE709) /* type = VRX VECTOR STORE ELEMENT (16) */ \ 1563 V(vsteg, VSTEG, 0xE70A) /* type = VRX VECTOR STORE ELEMENT (64) */ \ 1564 V(vstef, VSTEF, 0xE70B) /* type = VRX VECTOR STORE ELEMENT (32) */ \ 1565 V(vst, VST, 0xE70E) /* type = VRX VECTOR STORE */ 1566 1567 #define S390_RIE_G_OPCODE_LIST(V) \ 1568 V(lochi, LOCHI, \ 1569 0xEC42) /* type = RIE_G LOAD HALFWORD IMMEDIATE ON CONDITION (32<-16) */ \ 1570 V(locghi, LOCGHI, \ 1571 0xEC46) /* type = RIE_G LOAD HALFWORD IMMEDIATE ON CONDITION (64<-16) */ \ 1572 V(lochhi, LOCHHI, 0xEC4E) /* type = RIE_G LOAD HALFWORD HIGH IMMEDIATE */ \ 1573 /* ON CONDITION (32<-16) */ 1574 1575 #define S390_RRS_OPCODE_LIST(V) \ 1576 V(cgrb, CGRB, 0xECE4) /* type = RRS COMPARE AND BRANCH (64) */ \ 1577 V(clgrb, CLGRB, 0xECE5) /* type = RRS COMPARE LOGICAL AND BRANCH (64) */ \ 1578 V(crb, CRB, 0xECF6) /* type = RRS COMPARE AND BRANCH (32) */ \ 1579 V(clrb, CLRB, 0xECF7) /* type = RRS COMPARE LOGICAL AND BRANCH (32) */ 1580 1581 #define S390_OPCODE_LIST(V) \ 1582 S390_RSY_A_OPCODE_LIST(V) \ 1583 S390_RSY_B_OPCODE_LIST(V) \ 1584 S390_RXE_OPCODE_LIST(V) \ 1585 S390_RRF_A_OPCODE_LIST(V) \ 1586 S390_RXF_OPCODE_LIST(V) \ 1587 S390_IE_OPCODE_LIST(V) \ 1588 S390_RRF_B_OPCODE_LIST(V) \ 1589 S390_RRF_C_OPCODE_LIST(V) \ 1590 S390_MII_OPCODE_LIST(V) \ 1591 S390_RRF_D_OPCODE_LIST(V) \ 1592 S390_RRF_E_OPCODE_LIST(V) \ 1593 S390_VRR_A_OPCODE_LIST(V) \ 1594 S390_VRR_B_OPCODE_LIST(V) \ 1595 S390_VRR_C_OPCODE_LIST(V) \ 1596 S390_VRI_A_OPCODE_LIST(V) \ 1597 S390_VRR_D_OPCODE_LIST(V) \ 1598 S390_VRI_B_OPCODE_LIST(V) \ 1599 S390_VRR_E_OPCODE_LIST(V) \ 1600 S390_VRI_C_OPCODE_LIST(V) \ 1601 S390_VRI_D_OPCODE_LIST(V) \ 1602 S390_VRR_F_OPCODE_LIST(V) \ 1603 S390_RIS_OPCODE_LIST(V) \ 1604 S390_VRI_E_OPCODE_LIST(V) \ 1605 S390_RSL_A_OPCODE_LIST(V) \ 1606 S390_RSL_B_OPCODE_LIST(V) \ 1607 S390_SI_OPCODE_LIST(V) \ 1608 S390_SIL_OPCODE_LIST(V) \ 1609 S390_VRS_A_OPCODE_LIST(V) \ 1610 S390_RIL_A_OPCODE_LIST(V) \ 1611 S390_RIL_B_OPCODE_LIST(V) \ 1612 S390_VRS_B_OPCODE_LIST(V) \ 1613 S390_RIL_C_OPCODE_LIST(V) \ 1614 S390_VRS_C_OPCODE_LIST(V) \ 1615 S390_RI_A_OPCODE_LIST(V) \ 1616 S390_RSI_OPCODE_LIST(V) \ 1617 S390_RI_B_OPCODE_LIST(V) \ 1618 S390_RI_C_OPCODE_LIST(V) \ 1619 S390_SMI_OPCODE_LIST(V) \ 1620 S390_RXY_A_OPCODE_LIST(V) \ 1621 S390_RXY_B_OPCODE_LIST(V) \ 1622 S390_SIY_OPCODE_LIST(V) \ 1623 S390_SS_A_OPCODE_LIST(V) \ 1624 S390_E_OPCODE_LIST(V) \ 1625 S390_SS_B_OPCODE_LIST(V) \ 1626 S390_SS_C_OPCODE_LIST(V) \ 1627 S390_SS_D_OPCODE_LIST(V) \ 1628 S390_SS_E_OPCODE_LIST(V) \ 1629 S390_I_OPCODE_LIST(V) \ 1630 S390_SS_F_OPCODE_LIST(V) \ 1631 S390_SSE_OPCODE_LIST(V) \ 1632 S390_SSF_OPCODE_LIST(V) \ 1633 S390_RS_A_OPCODE_LIST(V) \ 1634 S390_RS_B_OPCODE_LIST(V) \ 1635 S390_S_OPCODE_LIST(V) \ 1636 S390_RX_A_OPCODE_LIST(V) \ 1637 S390_RX_B_OPCODE_LIST(V) \ 1638 S390_RIE_A_OPCODE_LIST(V) \ 1639 S390_RRD_OPCODE_LIST(V) \ 1640 S390_RIE_B_OPCODE_LIST(V) \ 1641 S390_RRE_OPCODE_LIST(V) \ 1642 S390_RIE_C_OPCODE_LIST(V) \ 1643 S390_RIE_D_OPCODE_LIST(V) \ 1644 S390_VRV_OPCODE_LIST(V) \ 1645 S390_RIE_E_OPCODE_LIST(V) \ 1646 S390_RR_OPCODE_LIST(V) \ 1647 S390_RIE_F_OPCODE_LIST(V) \ 1648 S390_VRX_OPCODE_LIST(V) \ 1649 S390_RIE_G_OPCODE_LIST(V) \ 1650 S390_RRS_OPCODE_LIST(V) 1651 1652 // Opcodes as defined in Appendix B-2 table 1653 enum Opcode { 1654 #define DECLARE_OPCODES(name, opcode_name, opcode_value) \ 1655 opcode_name = opcode_value, 1656 S390_OPCODE_LIST(DECLARE_OPCODES) 1657 #undef DECLARE_OPCODES 1658 1659 BKPT = 0x0001, // GDB Software Breakpoint 1660 DUMY = 0xE352 // Special dummy opcode 1661 }; 1662 1663 // Instruction encoding bits and masks. 1664 enum { 1665 // Instruction encoding bit 1666 B1 = 1 << 1, 1667 B4 = 1 << 4, 1668 B5 = 1 << 5, 1669 B7 = 1 << 7, 1670 B8 = 1 << 8, 1671 B9 = 1 << 9, 1672 B12 = 1 << 12, 1673 B18 = 1 << 18, 1674 B19 = 1 << 19, 1675 B20 = 1 << 20, 1676 B22 = 1 << 22, 1677 B23 = 1 << 23, 1678 B24 = 1 << 24, 1679 B25 = 1 << 25, 1680 B26 = 1 << 26, 1681 B27 = 1 << 27, 1682 B28 = 1 << 28, 1683 1684 B6 = 1 << 6, 1685 B10 = 1 << 10, 1686 B11 = 1 << 11, 1687 B16 = 1 << 16, 1688 B17 = 1 << 17, 1689 B21 = 1 << 21, 1690 1691 // Instruction bit masks 1692 kCondMask = 0x1F << 21, 1693 kOff12Mask = (1 << 12) - 1, 1694 kImm24Mask = (1 << 24) - 1, 1695 kOff16Mask = (1 << 16) - 1, 1696 kImm16Mask = (1 << 16) - 1, 1697 kImm26Mask = (1 << 26) - 1, 1698 kBOfieldMask = 0x1f << 21, 1699 kOpcodeMask = 0x3f << 26, 1700 kExt2OpcodeMask = 0x1f << 1, 1701 kExt5OpcodeMask = 0x3 << 2, 1702 kBIMask = 0x1F << 16, 1703 kBDMask = 0x14 << 2, 1704 kAAMask = 0x01 << 1, 1705 kLKMask = 0x01, 1706 kRCMask = 0x01, 1707 kTOMask = 0x1f << 21 1708 }; 1709 1710 // S390 instructions requires bigger shifts, 1711 // make them macros instead of enum because of the typing issue 1712 #define B32 ((uint64_t)1 << 32) 1713 #define B36 ((uint64_t)1 << 36) 1714 #define B40 ((uint64_t)1 << 40) 1715 const FourByteInstr kFourByteBrCondMask = 0xF << 20; 1716 const SixByteInstr kSixByteBrCondMask = static_cast<SixByteInstr>(0xF) << 36; 1717 1718 // ----------------------------------------------------------------------------- 1719 // Addressing modes and instruction variants. 1720 1721 // Overflow Exception 1722 enum OEBit { 1723 SetOE = 1 << 10, // Set overflow exception 1724 LeaveOE = 0 << 10 // No overflow exception 1725 }; 1726 1727 // Record bit 1728 enum RCBit { // Bit 0 1729 SetRC = 1, // LT,GT,EQ,SO 1730 LeaveRC = 0 // None 1731 }; 1732 1733 // Link bit 1734 enum LKBit { // Bit 0 1735 SetLK = 1, // Load effective address of next instruction 1736 LeaveLK = 0 // No action 1737 }; 1738 1739 enum BOfield { // Bits 25-21 1740 DCBNZF = 0 << 21, // Decrement CTR; branch if CTR != 0 and condition false 1741 DCBEZF = 2 << 21, // Decrement CTR; branch if CTR == 0 and condition false 1742 BF = 4 << 21, // Branch if condition false 1743 DCBNZT = 8 << 21, // Decrement CTR; branch if CTR != 0 and condition true 1744 DCBEZT = 10 << 21, // Decrement CTR; branch if CTR == 0 and condition true 1745 BT = 12 << 21, // Branch if condition true 1746 DCBNZ = 16 << 21, // Decrement CTR; branch if CTR != 0 1747 DCBEZ = 18 << 21, // Decrement CTR; branch if CTR == 0 1748 BA = 20 << 21 // Branch always 1749 }; 1750 1751 #ifdef _AIX 1752 #undef CR_LT 1753 #undef CR_GT 1754 #undef CR_EQ 1755 #undef CR_SO 1756 #endif 1757 1758 enum CRBit { CR_LT = 0, CR_GT = 1, CR_EQ = 2, CR_SO = 3, CR_FU = 3 }; 1759 1760 #define CRWIDTH 4 1761 1762 // ----------------------------------------------------------------------------- 1763 // Supervisor Call (svc) specific support. 1764 1765 // Special Software Interrupt codes when used in the presence of the S390 1766 // simulator. 1767 // SVC provides a 24bit immediate value. Use bits 22:0 for standard 1768 // SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 1769 enum SoftwareInterruptCodes { 1770 // Transition to C code 1771 kCallRtRedirected = 0x0010, 1772 // Breakpoint 1773 kBreakpoint = 0x0000, 1774 // Stop 1775 kStopCode = 1 << 23 1776 }; 1777 const uint32_t kStopCodeMask = kStopCode - 1; 1778 const uint32_t kMaxStopCode = kStopCode - 1; 1779 const int32_t kDefaultStopCode = -1; 1780 1781 // FP rounding modes. 1782 enum FPRoundingMode { 1783 RN = 0, // Round to Nearest. 1784 RZ = 1, // Round towards zero. 1785 RP = 2, // Round towards Plus Infinity. 1786 RM = 3, // Round towards Minus Infinity. 1787 1788 // Aliases. 1789 kRoundToNearest = RN, 1790 kRoundToZero = RZ, 1791 kRoundToPlusInf = RP, 1792 kRoundToMinusInf = RM 1793 }; 1794 1795 const uint32_t kFPRoundingModeMask = 3; 1796 1797 enum CheckForInexactConversion { 1798 kCheckForInexactConversion, 1799 kDontCheckForInexactConversion 1800 }; 1801 1802 // ----------------------------------------------------------------------------- 1803 // Specific instructions, constants, and masks. 1804 1805 // use TRAP4 to indicate redirection call for simulation mode 1806 const Instr rtCallRedirInstr = TRAP4; 1807 1808 // ----------------------------------------------------------------------------- 1809 // Instruction abstraction. 1810 1811 // The class Instruction enables access to individual fields defined in the 1812 // z/Architecture instruction set encoding. 1813 class Instruction { 1814 public: 1815 // S390 Opcode Format Types 1816 // Based on the first byte of the opcode, we can determine how to extract 1817 // the entire opcode of the instruction. The various favours include: 1818 enum OpcodeFormatType { 1819 ONE_BYTE_OPCODE, // One Byte - Bits 0 to 7 1820 TWO_BYTE_OPCODE, // Two Bytes - Bits 0 to 15 1821 TWO_BYTE_DISJOINT_OPCODE, // Two Bytes - Bits 0 to 7, 40 to 47 1822 THREE_NIBBLE_OPCODE // Three Nibbles - Bits 0 to 7, 12 to 15 1823 }; 1824 1825 static OpcodeFormatType OpcodeFormatTable[256]; 1826 // Helper macro to define static accessors. 1827 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 1828 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 1829 static inline return_type Name(Instr instr) { \ 1830 char* temp = reinterpret_cast<char*>(&instr); \ 1831 return reinterpret_cast<Instruction*>(temp)->Name(); \ 1832 } 1833 1834 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 1835 1836 // Get the raw instruction bits. 1837 template <typename T> 1838 inline T InstructionBits() const { 1839 return Instruction::InstructionBits<T>(reinterpret_cast<const byte*>(this)); 1840 } 1841 inline Instr InstructionBits() const { 1842 return *reinterpret_cast<const Instr*>(this); 1843 } 1844 1845 // Set the raw instruction bits to value. 1846 template <typename T> 1847 inline void SetInstructionBits(T value) const { 1848 Instruction::SetInstructionBits<T>(reinterpret_cast<const byte*>(this), 1849 value); 1850 } 1851 inline void SetInstructionBits(Instr value) { 1852 *reinterpret_cast<Instr*>(this) = value; 1853 } 1854 1855 // Read one particular bit out of the instruction bits. 1856 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } 1857 1858 // Read a bit field's value out of the instruction bits. 1859 inline int Bits(int hi, int lo) const { 1860 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 1861 } 1862 1863 // Read bits according to instruction type 1864 template <typename T, typename U> 1865 inline U Bits(int hi, int lo) const { 1866 return (InstructionBits<T>() >> lo) & ((2 << (hi - lo)) - 1); 1867 } 1868 1869 // Read a bit field out of the instruction bits. 1870 inline int BitField(int hi, int lo) const { 1871 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 1872 } 1873 1874 // Determine the instruction length 1875 inline int InstructionLength() { 1876 return Instruction::InstructionLength(reinterpret_cast<const byte*>(this)); 1877 } 1878 // Extract the Instruction Opcode 1879 inline Opcode S390OpcodeValue() { 1880 return Instruction::S390OpcodeValue(reinterpret_cast<const byte*>(this)); 1881 } 1882 1883 // Static support. 1884 1885 // Read one particular bit out of the instruction bits. 1886 static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; } 1887 1888 // Read the value of a bit field out of the instruction bits. 1889 static inline int Bits(Instr instr, int hi, int lo) { 1890 return (instr >> lo) & ((2 << (hi - lo)) - 1); 1891 } 1892 1893 // Read a bit field out of the instruction bits. 1894 static inline int BitField(Instr instr, int hi, int lo) { 1895 return instr & (((2 << (hi - lo)) - 1) << lo); 1896 } 1897 1898 // Determine the instruction length of the given instruction 1899 static inline int InstructionLength(const byte* instr) { 1900 // Length can be determined by the first nibble. 1901 // 0x0 to 0x3 => 2-bytes 1902 // 0x4 to 0xB => 4-bytes 1903 // 0xC to 0xF => 6-bytes 1904 byte topNibble = (*instr >> 4) & 0xF; 1905 if (topNibble <= 3) 1906 return 2; 1907 else if (topNibble <= 0xB) 1908 return 4; 1909 return 6; 1910 } 1911 1912 // Returns the instruction bits of the given instruction 1913 static inline uint64_t InstructionBits(const byte* instr) { 1914 int length = InstructionLength(instr); 1915 if (2 == length) 1916 return static_cast<uint64_t>(InstructionBits<TwoByteInstr>(instr)); 1917 else if (4 == length) 1918 return static_cast<uint64_t>(InstructionBits<FourByteInstr>(instr)); 1919 else 1920 return InstructionBits<SixByteInstr>(instr); 1921 } 1922 1923 // Extract the raw instruction bits 1924 template <typename T> 1925 static inline T InstructionBits(const byte* instr) { 1926 #if !V8_TARGET_LITTLE_ENDIAN 1927 if (sizeof(T) <= 4) { 1928 return *reinterpret_cast<const T*>(instr); 1929 } else { 1930 // We cannot read 8-byte instructon address directly, because for a 1931 // six-byte instruction, the extra 2-byte address might not be 1932 // allocated. 1933 uint64_t fourBytes = *reinterpret_cast<const uint32_t*>(instr); 1934 uint16_t twoBytes = *reinterpret_cast<const uint16_t*>(instr + 4); 1935 return (fourBytes << 16 | twoBytes); 1936 } 1937 #else 1938 // Even on little endian hosts (simulation), the instructions 1939 // are stored as big-endian in order to decode the opcode and 1940 // instruction length. 1941 T instr_bits = 0; 1942 1943 // 6-byte instrs are represented by uint64_t 1944 uint32_t size = (sizeof(T) == 8) ? 6 : sizeof(T); 1945 1946 for (T i = 0; i < size; i++) { 1947 instr_bits <<= 8; 1948 instr_bits |= *(instr + i); 1949 } 1950 return instr_bits; 1951 #endif 1952 } 1953 1954 // Set the Instruction Bits to value 1955 template <typename T> 1956 static inline void SetInstructionBits(byte* instr, T value) { 1957 #if V8_TARGET_LITTLE_ENDIAN 1958 // The instruction bits are stored in big endian format even on little 1959 // endian hosts, in order to decode instruction length and opcode. 1960 // The following code will reverse the bytes so that the stores later 1961 // (which are in native endianess) will effectively save the instruction 1962 // in big endian. 1963 if (sizeof(T) == 2) { 1964 // Two Byte Instruction 1965 value = ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); 1966 } else if (sizeof(T) == 4) { 1967 // Four Byte Instruction 1968 value = ((value & 0x000000FF) << 24) | ((value & 0x0000FF00) << 8) | 1969 ((value & 0x00FF0000) >> 8) | ((value & 0xFF000000) >> 24); 1970 } else if (sizeof(T) == 8) { 1971 // Six Byte Instruction 1972 uint64_t orig_value = static_cast<uint64_t>(value); 1973 value = (static_cast<uint64_t>(orig_value & 0xFF) << 40) | 1974 (static_cast<uint64_t>((orig_value >> 8) & 0xFF) << 32) | 1975 (static_cast<uint64_t>((orig_value >> 16) & 0xFF) << 24) | 1976 (static_cast<uint64_t>((orig_value >> 24) & 0xFF) << 16) | 1977 (static_cast<uint64_t>((orig_value >> 32) & 0xFF) << 8) | 1978 (static_cast<uint64_t>((orig_value >> 40) & 0xFF)); 1979 } 1980 #endif 1981 if (sizeof(T) <= 4) { 1982 *reinterpret_cast<T*>(instr) = value; 1983 } else { 1984 #if V8_TARGET_LITTLE_ENDIAN 1985 uint64_t orig_value = static_cast<uint64_t>(value); 1986 *reinterpret_cast<uint32_t*>(instr) = static_cast<uint32_t>(value); 1987 *reinterpret_cast<uint16_t*>(instr + 4) = 1988 static_cast<uint16_t>((orig_value >> 32) & 0xFFFF); 1989 #else 1990 *reinterpret_cast<uint32_t*>(instr) = static_cast<uint32_t>(value >> 16); 1991 *reinterpret_cast<uint16_t*>(instr + 4) = 1992 static_cast<uint16_t>(value & 0xFFFF); 1993 #endif 1994 } 1995 } 1996 1997 // Get Instruction Format Type 1998 static OpcodeFormatType getOpcodeFormatType(const byte* instr) { 1999 const byte firstByte = *instr; 2000 return OpcodeFormatTable[firstByte]; 2001 } 2002 2003 // Extract the full opcode from the instruction. 2004 static inline Opcode S390OpcodeValue(const byte* instr) { 2005 OpcodeFormatType opcodeType = getOpcodeFormatType(instr); 2006 2007 // The native instructions are encoded in big-endian format 2008 // even if running on little-endian host. Hence, we need 2009 // to ensure we use byte* based bit-wise logic. 2010 switch (opcodeType) { 2011 case ONE_BYTE_OPCODE: 2012 // One Byte - Bits 0 to 7 2013 return static_cast<Opcode>(*instr); 2014 case TWO_BYTE_OPCODE: 2015 // Two Bytes - Bits 0 to 15 2016 return static_cast<Opcode>((*instr << 8) | (*(instr + 1))); 2017 case TWO_BYTE_DISJOINT_OPCODE: 2018 // Two Bytes - Bits 0 to 7, 40 to 47 2019 return static_cast<Opcode>((*instr << 8) | (*(instr + 5) & 0xFF)); 2020 default: 2021 // case THREE_NIBBLE_OPCODE: 2022 // Three Nibbles - Bits 0 to 7, 12 to 15 2023 return static_cast<Opcode>((*instr << 4) | (*(instr + 1) & 0xF)); 2024 } 2025 2026 UNREACHABLE(); 2027 } 2028 2029 // Fields used in Software interrupt instructions 2030 inline SoftwareInterruptCodes SvcValue() const { 2031 return static_cast<SoftwareInterruptCodes>(Bits<FourByteInstr, int>(15, 0)); 2032 } 2033 2034 // Instructions are read of out a code stream. The only way to get a 2035 // reference to an instruction is to convert a pointer. There is no way 2036 // to allocate or create instances of class Instruction. 2037 // Use the At(pc) function to create references to Instruction. 2038 static Instruction* At(byte* pc) { 2039 return reinterpret_cast<Instruction*>(pc); 2040 } 2041 2042 private: 2043 // We need to prevent the creation of instances of class Instruction. 2044 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 2045 }; 2046 2047 #define DECLARE_FIELD_FOR_TWO_BYTE_INSTR(name, T, lo, hi) \ 2048 inline int name() const { \ 2049 return Bits<TwoByteInstr, T>(15 - (lo), 15 - (hi) + 1); \ 2050 } 2051 2052 #define DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(name, T, lo, hi) \ 2053 inline int name() const { \ 2054 return Bits<FourByteInstr, T>(31 - (lo), 31 - (hi) + 1); \ 2055 } 2056 2057 #define DECLARE_FIELD_FOR_SIX_BYTE_INSTR(name, T, lo, hi) \ 2058 inline int name() const { \ 2059 return Bits<SixByteInstr, T>(47 - (lo), 47 - (hi) + 1); \ 2060 } 2061 2062 class TwoByteInstruction : public Instruction { 2063 public: 2064 inline int size() const { return 2; } 2065 }; 2066 2067 class FourByteInstruction : public Instruction { 2068 public: 2069 inline int size() const { return 4; } 2070 }; 2071 2072 class SixByteInstruction : public Instruction { 2073 public: 2074 inline int size() const { return 6; } 2075 }; 2076 2077 // I Instruction 2078 class IInstruction : public TwoByteInstruction { 2079 public: 2080 DECLARE_FIELD_FOR_TWO_BYTE_INSTR(IValue, int, 8, 16); 2081 }; 2082 2083 // E Instruction 2084 class EInstruction : public TwoByteInstruction {}; 2085 2086 // IE Instruction 2087 class IEInstruction : public FourByteInstruction { 2088 public: 2089 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I1Value, int, 24, 28); 2090 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I2Value, int, 28, 32); 2091 }; 2092 2093 // MII Instruction 2094 class MIIInstruction : public SixByteInstruction { 2095 public: 2096 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M1Value, uint32_t, 8, 12); 2097 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(RI2Value, int, 12, 24); 2098 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(RI3Value, int, 24, 47); 2099 }; 2100 2101 // RI Instruction 2102 class RIInstruction : public FourByteInstruction { 2103 public: 2104 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(R1Value, int, 8, 12); 2105 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I2Value, int, 16, 32); 2106 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I2UnsignedValue, uint32_t, 16, 32); 2107 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(M1Value, uint32_t, 8, 12); 2108 }; 2109 2110 // RR Instruction 2111 class RRInstruction : Instruction { 2112 public: 2113 inline int R1Value() const { 2114 // the high and low parameters of Bits is the number of bits from 2115 // rightmost place 2116 return Bits<TwoByteInstr, int>(7, 4); 2117 } 2118 inline int R2Value() const { return Bits<TwoByteInstr, int>(3, 0); } 2119 inline Condition M1Value() const { 2120 return static_cast<Condition>(Bits<TwoByteInstr, int>(7, 4)); 2121 } 2122 2123 inline int size() const { return 2; } 2124 }; 2125 2126 // RRE Instruction 2127 class RREInstruction : Instruction { 2128 public: 2129 inline int R1Value() const { return Bits<FourByteInstr, int>(7, 4); } 2130 inline int R2Value() const { return Bits<FourByteInstr, int>(3, 0); } 2131 inline int M3Value() const { return Bits<FourByteInstr, int>(15, 12); } 2132 inline int M4Value() const { return Bits<FourByteInstr, int>(19, 16); } 2133 inline int size() const { return 4; } 2134 }; 2135 2136 // RRF Instruction 2137 class RRFInstruction : Instruction { 2138 public: 2139 inline int R1Value() const { return Bits<FourByteInstr, int>(7, 4); } 2140 inline int R2Value() const { return Bits<FourByteInstr, int>(3, 0); } 2141 inline int R3Value() const { return Bits<FourByteInstr, int>(15, 12); } 2142 inline int M3Value() const { return Bits<FourByteInstr, int>(15, 12); } 2143 inline int M4Value() const { return Bits<FourByteInstr, int>(11, 8); } 2144 inline int size() const { return 4; } 2145 }; 2146 2147 // RRD Isntruction 2148 class RRDInstruction : Instruction { 2149 public: 2150 inline int R1Value() const { return Bits<FourByteInstr, int>(15, 12); } 2151 inline int R2Value() const { return Bits<FourByteInstr, int>(3, 0); } 2152 inline int R3Value() const { return Bits<FourByteInstr, int>(7, 4); } 2153 inline int size() const { return 4; } 2154 }; 2155 2156 // RS Instruction 2157 class RSInstruction : Instruction { 2158 public: 2159 inline int R1Value() const { return Bits<FourByteInstr, int>(23, 20); } 2160 inline int R3Value() const { return Bits<FourByteInstr, int>(19, 16); } 2161 inline int B2Value() const { return Bits<FourByteInstr, int>(15, 12); } 2162 inline unsigned int D2Value() const { 2163 return Bits<FourByteInstr, unsigned int>(11, 0); 2164 } 2165 inline int size() const { return 4; } 2166 }; 2167 2168 // RSI Instruction 2169 class RSIInstruction : Instruction { 2170 public: 2171 inline int R1Value() const { return Bits<FourByteInstr, int>(23, 20); } 2172 inline int R3Value() const { return Bits<FourByteInstr, int>(19, 16); } 2173 inline int I2Value() const { 2174 return static_cast<int32_t>(Bits<FourByteInstr, int16_t>(15, 0)); 2175 } 2176 inline int size() const { return 4; } 2177 }; 2178 2179 // RSY Instruction 2180 class RSYInstruction : Instruction { 2181 public: 2182 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2183 inline int R3Value() const { return Bits<SixByteInstr, int>(35, 32); } 2184 inline int B2Value() const { return Bits<SixByteInstr, int>(31, 28); } 2185 inline int32_t D2Value() const { 2186 int32_t value = Bits<SixByteInstr, int32_t>(27, 16); 2187 value += Bits<SixByteInstr, int8_t>(15, 8) << 12; 2188 return value; 2189 } 2190 inline int size() const { return 6; } 2191 }; 2192 2193 // RX Instruction 2194 class RXInstruction : Instruction { 2195 public: 2196 inline int R1Value() const { return Bits<FourByteInstr, int>(23, 20); } 2197 inline int X2Value() const { return Bits<FourByteInstr, int>(19, 16); } 2198 inline int B2Value() const { return Bits<FourByteInstr, int>(15, 12); } 2199 inline uint32_t D2Value() const { 2200 return Bits<FourByteInstr, uint32_t>(11, 0); 2201 } 2202 inline int size() const { return 4; } 2203 }; 2204 2205 // RXY Instruction 2206 class RXYInstruction : Instruction { 2207 public: 2208 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2209 inline int X2Value() const { return Bits<SixByteInstr, int>(35, 32); } 2210 inline int B2Value() const { return Bits<SixByteInstr, int>(31, 28); } 2211 inline int32_t D2Value() const { 2212 int32_t value = Bits<SixByteInstr, uint32_t>(27, 16); 2213 value += Bits<SixByteInstr, int8_t>(15, 8) << 12; 2214 return value; 2215 } 2216 inline int size() const { return 6; } 2217 }; 2218 2219 // RIL Instruction 2220 class RILInstruction : Instruction { 2221 public: 2222 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2223 inline int32_t I2Value() const { return Bits<SixByteInstr, int32_t>(31, 0); } 2224 inline uint32_t I2UnsignedValue() const { 2225 return Bits<SixByteInstr, uint32_t>(31, 0); 2226 } 2227 inline int size() const { return 6; } 2228 }; 2229 2230 // SI Instruction 2231 class SIInstruction : Instruction { 2232 public: 2233 inline int B1Value() const { return Bits<FourByteInstr, int>(15, 12); } 2234 inline uint32_t D1Value() const { 2235 return Bits<FourByteInstr, uint32_t>(11, 0); 2236 } 2237 inline uint8_t I2Value() const { 2238 return Bits<FourByteInstr, uint8_t>(23, 16); 2239 } 2240 inline int size() const { return 4; } 2241 }; 2242 2243 // SIY Instruction 2244 class SIYInstruction : Instruction { 2245 public: 2246 inline int B1Value() const { return Bits<SixByteInstr, int>(31, 28); } 2247 inline int32_t D1Value() const { 2248 int32_t value = Bits<SixByteInstr, uint32_t>(27, 16); 2249 value += Bits<SixByteInstr, int8_t>(15, 8) << 12; 2250 return value; 2251 } 2252 inline uint8_t I2Value() const { return Bits<SixByteInstr, uint8_t>(39, 32); } 2253 inline int size() const { return 6; } 2254 }; 2255 2256 // SIL Instruction 2257 class SILInstruction : Instruction { 2258 public: 2259 inline int B1Value() const { return Bits<SixByteInstr, int>(31, 28); } 2260 inline int D1Value() const { return Bits<SixByteInstr, int>(27, 16); } 2261 inline int I2Value() const { return Bits<SixByteInstr, int>(15, 0); } 2262 inline int size() const { return 6; } 2263 }; 2264 2265 // SS Instruction 2266 class SSInstruction : Instruction { 2267 public: 2268 inline int B1Value() const { return Bits<SixByteInstr, int>(31, 28); } 2269 inline int B2Value() const { return Bits<SixByteInstr, int>(15, 12); } 2270 inline int D1Value() const { return Bits<SixByteInstr, int>(27, 16); } 2271 inline int D2Value() const { return Bits<SixByteInstr, int>(11, 0); } 2272 inline int Length() const { return Bits<SixByteInstr, int>(39, 32); } 2273 inline int size() const { return 6; } 2274 }; 2275 2276 // RXE Instruction 2277 class RXEInstruction : Instruction { 2278 public: 2279 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2280 inline int X2Value() const { return Bits<SixByteInstr, int>(35, 32); } 2281 inline int B2Value() const { return Bits<SixByteInstr, int>(31, 28); } 2282 inline int D2Value() const { return Bits<SixByteInstr, int>(27, 16); } 2283 inline int size() const { return 6; } 2284 }; 2285 2286 // RIE Instruction 2287 class RIEInstruction : Instruction { 2288 public: 2289 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2290 inline int R2Value() const { return Bits<SixByteInstr, int>(35, 32); } 2291 inline int I3Value() const { return Bits<SixByteInstr, uint32_t>(31, 24); } 2292 inline int I4Value() const { return Bits<SixByteInstr, uint32_t>(23, 16); } 2293 inline int I5Value() const { return Bits<SixByteInstr, uint32_t>(15, 8); } 2294 inline int I6Value() const { 2295 return static_cast<int32_t>(Bits<SixByteInstr, int16_t>(31, 16)); 2296 } 2297 inline int size() const { return 6; } 2298 }; 2299 2300 // VRR Instruction 2301 class VRR_C_Instruction : SixByteInstruction { 2302 public: 2303 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R1Value, int, 8, 12); 2304 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R2Value, int, 12, 16); 2305 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R3Value, int, 16, 20); 2306 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M6Value, uint32_t, 24, 28); 2307 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M5Value, uint32_t, 28, 32); 2308 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M4Value, uint32_t, 32, 36); 2309 }; 2310 2311 // Helper functions for converting between register numbers and names. 2312 class Registers { 2313 public: 2314 // Lookup the register number for the name provided. 2315 static int Number(const char* name); 2316 2317 private: 2318 static const char* names_[kNumRegisters]; 2319 }; 2320 2321 // Helper functions for converting between FP register numbers and names. 2322 class DoubleRegisters { 2323 public: 2324 // Lookup the register number for the name provided. 2325 static int Number(const char* name); 2326 2327 private: 2328 static const char* names_[kNumDoubleRegisters]; 2329 }; 2330 2331 } // namespace internal 2332 } // namespace v8 2333 2334 #endif // V8_S390_CONSTANTS_S390_H_ 2335
