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Searched
defs:SITargetLowering
(Results
1 - 2
of
2
) sorted by null
/external/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp
55
SITargetLowering
::
SITargetLowering
(const TargetMachine &TM,
258
const SISubtarget *
SITargetLowering
::getSubtarget() const {
266
bool
SITargetLowering
::getTgtMemIntrinsic(IntrinsicInfo &Info,
285
bool
SITargetLowering
::isShuffleMaskLegal(const SmallVectorImpl<int> &,
292
bool
SITargetLowering
::isLegalFlatAddressingMode(const AddrMode &AM) const {
298
bool
SITargetLowering
::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
333
bool
SITargetLowering
::isLegalAddressingMode(const DataLayout &DL,
429
bool
SITargetLowering
::allowsMisalignedMemoryAccesses(EVT VT,
477
EVT
SITargetLowering
::getOptimalMemOpType(uint64_t Size, unsigned DstAlign
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp
114
SITargetLowering
::
SITargetLowering
(const TargetMachine &TM,
671
const GCNSubtarget *
SITargetLowering
::getSubtarget() const {
683
bool
SITargetLowering
::isFPExtFoldable(unsigned Opcode,
691
bool
SITargetLowering
::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
697
MVT
SITargetLowering
::getRegisterTypeForCallingConv(LLVMContext &Context,
719
unsigned
SITargetLowering
::getNumRegistersForCallingConv(LLVMContext &Context,
741
unsigned
SITargetLowering
::getVectorTypeBreakdownForCallingConv(
778
bool
SITargetLowering
::getTgtMemIntrinsic(IntrinsicInfo &Info,
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all
...]
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