| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCodeEmitter.cpp | 140 unsigned SOffset = 0;
152 ++SOffset;
179 HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| GCNHazardRecognizer.cpp | 505 // instruction is not using a register in the soffset field.
506 const MachineOperand *SOffset =
507 TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
508 // If we have no soffset operand, then assume this field has been
511 (!SOffset || !SOffset->isReg()))
|
| SIRegisterInfo.cpp | 359 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() ==
501 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset))
536 unsigned SOffset = ScratchOffsetReg;
551 SOffset = AMDGPU::NoRegister;
561 SOffset = RS->FindUnusedReg(&AMDGPU::SGPR_32RegClass);
563 if (SOffset == AMDGPU::NoRegister) {
571 SOffset = ScratchOffsetReg;
577 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
604 .addReg(SOffset, SOffsetRegState)
801 .addReg(MFI->getFrameOffsetReg()) // soffset
[all...] |
| AMDGPUISelDAGToDAG.cpp | 120 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
124 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
127 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
131 SDValue &SOffset, SDValue &ImmOffset) const;
133 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
136 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
139 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
141 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
144 SDValue &SOffset,
146 bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
[all...] |
| SIInstrInfo.cpp | 222 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
323 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset);
324 if (SOffset && SOffset->isReg())
337 if (SOffset) // soffset can be an inline immediate.
338 Offset += SOffset->getImm();
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 430 unsigned SOffset = ScratchOffset;
437 SOffset = AMDGPU::NoRegister;
442 SOffset = RS->FindUnusedReg(&AMDGPU::SGPR_32RegClass);
444 if (SOffset == AMDGPU::NoRegister) {
453 SOffset = ScratchOffset;
457 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
479 .addReg(SOffset, SOffsetRegState)
[all...] |
| AMDGPUISelDAGToDAG.cpp | 93 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
97 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
100 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
103 SDValue &SOffset, SDValue &ImmOffset) const;
104 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
107 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
109 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
112 SDValue &SOffset,
114 bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
116 bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 294 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
296 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 445 int SOffset = Offset;
492 MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset,
504 MergeOpsUpdate(MBB, MemOps, SIndex, MemOps.size(), insertAfter, SOffset,
[all...] |
