1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * 4 * BRIEF MODULE DESCRIPTION 5 * Include file for Alchemy Semiconductor's Au1k CPU. 6 * 7 * Copyright 2000,2001 MontaVista Software Inc. 8 * Author: MontaVista Software, Inc. 9 * ppopov (at) mvista.com or source (at) mvista.com 10 */ 11 12 /* 13 * some definitions add by takuzo (at) sm.sony.co.jp and sato (at) sm.sony.co.jp 14 */ 15 16 #ifndef _AU1X00_H_ 17 #define _AU1X00_H_ 18 19 #ifndef __ASSEMBLY__ 20 /* cpu pipeline flush */ 21 void static inline au_sync(void) 22 { 23 __asm__ volatile ("sync"); 24 } 25 26 void static inline au_sync_udelay(int us) 27 { 28 __asm__ volatile ("sync"); 29 udelay(us); 30 } 31 32 void static inline au_writeb(u8 val, int reg) 33 { 34 *(volatile u8 *)(reg) = val; 35 } 36 37 void static inline au_writew(u16 val, int reg) 38 { 39 *(volatile u16 *)(reg) = val; 40 } 41 42 void static inline au_writel(u32 val, int reg) 43 { 44 *(volatile u32 *)(reg) = val; 45 } 46 47 static inline u8 au_readb(unsigned long port) 48 { 49 return (*(volatile u8 *)port); 50 } 51 52 static inline u16 au_readw(unsigned long port) 53 { 54 return (*(volatile u16 *)port); 55 } 56 57 static inline u32 au_readl(unsigned long port) 58 { 59 return (*(volatile u32 *)port); 60 } 61 62 /* These next three functions should be a generic part of the MIPS 63 * kernel (with the 'au_' removed from the name) and selected for 64 * processors that support the instructions. 65 * Taken from PPC tree. -- Dan 66 */ 67 /* Return the bit position of the most significant 1 bit in a word */ 68 static __inline__ int __ilog2(unsigned int x) 69 { 70 int lz; 71 72 asm volatile ( 73 ".set\tnoreorder\n\t" 74 ".set\tnoat\n\t" 75 ".set\tmips32\n\t" 76 "clz\t%0,%1\n\t" 77 ".set\tmips0\n\t" 78 ".set\tat\n\t" 79 ".set\treorder" 80 : "=r" (lz) 81 : "r" (x)); 82 83 return 31 - lz; 84 } 85 86 static __inline__ int au_ffz(unsigned int x) 87 { 88 if ((x = ~x) == 0) 89 return 32; 90 return __ilog2(x & -x); 91 } 92 93 /* 94 * ffs: find first bit set. This is defined the same way as 95 * the libc and compiler builtin ffs routines, therefore 96 * differs in spirit from the above ffz (man ffs). 97 */ 98 static __inline__ int au_ffs(int x) 99 { 100 return __ilog2(x & -x) + 1; 101 } 102 103 #define gpio_set(Value) outl(Value, SYS_OUTPUTSET) 104 #define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR) 105 #define gpio_read() inl(SYS_PINSTATERD) 106 #define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR) 107 108 #endif /* !ASSEMBLY */ 109 110 #ifdef CONFIG_PM 111 /* no CP0 timer irq */ 112 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) 113 #else 114 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 115 #endif 116 117 #define CP0_IWATCHLO $18,1 118 #define CP0_DEBUG $23 119 120 /* SDRAM Controller */ 121 #ifdef CONFIG_SOC_AU1550 122 123 #define MEM_SDMODE0 0xB4000800 124 #define MEM_SDMODE1 0xB4000808 125 #define MEM_SDMODE2 0xB4000810 126 127 #define MEM_SDADDR0 0xB4000820 128 #define MEM_SDADDR1 0xB4000828 129 #define MEM_SDADDR2 0xB4000830 130 131 #define MEM_SDCONFIGA 0xB4000840 132 #define MEM_SDCONFIGB 0xB4000848 133 #define MEM_SDPRECMD 0xB40008c0 134 #define MEM_SDAUTOREF 0xB40008c8 135 136 #define MEM_SDWRMD0 0xB4000880 137 #define MEM_SDWRMD1 0xB4000888 138 #define MEM_SDWRMD2 0xB4000890 139 140 #else /* CONFIG_SOC_AU1550 */ 141 142 #define MEM_SDMODE0 0xB4000000 143 #define MEM_SDMODE1 0xB4000004 144 #define MEM_SDMODE2 0xB4000008 145 146 #define MEM_SDADDR0 0xB400000C 147 #define MEM_SDADDR1 0xB4000010 148 #define MEM_SDADDR2 0xB4000014 149 150 #define MEM_SDREFCFG 0xB4000018 151 #define MEM_SDPRECMD 0xB400001C 152 #define MEM_SDAUTOREF 0xB4000020 153 154 #define MEM_SDWRMD0 0xB4000024 155 #define MEM_SDWRMD1 0xB4000028 156 #define MEM_SDWRMD2 0xB400002C 157 158 #endif /* CONFIG_SOC_AU1550 */ 159 160 #define MEM_SDSLEEP 0xB4000030 161 #define MEM_SDSMCKE 0xB4000034 162 163 /* Static Bus Controller */ 164 #define MEM_STCFG0 0xB4001000 165 #define MEM_STTIME0 0xB4001004 166 #define MEM_STADDR0 0xB4001008 167 168 #define MEM_STCFG1 0xB4001010 169 #define MEM_STTIME1 0xB4001014 170 #define MEM_STADDR1 0xB4001018 171 172 #define MEM_STCFG2 0xB4001020 173 #define MEM_STTIME2 0xB4001024 174 #define MEM_STADDR2 0xB4001028 175 176 #define MEM_STCFG3 0xB4001030 177 #define MEM_STTIME3 0xB4001034 178 #define MEM_STADDR3 0xB4001038 179 180 /* Interrupt Controller 0 */ 181 #define IC0_CFG0RD 0xB0400040 182 #define IC0_CFG0SET 0xB0400040 183 #define IC0_CFG0CLR 0xB0400044 184 185 #define IC0_CFG1RD 0xB0400048 186 #define IC0_CFG1SET 0xB0400048 187 #define IC0_CFG1CLR 0xB040004C 188 189 #define IC0_CFG2RD 0xB0400050 190 #define IC0_CFG2SET 0xB0400050 191 #define IC0_CFG2CLR 0xB0400054 192 193 #define IC0_REQ0INT 0xB0400054 194 #define IC0_SRCRD 0xB0400058 195 #define IC0_SRCSET 0xB0400058 196 #define IC0_SRCCLR 0xB040005C 197 #define IC0_REQ1INT 0xB040005C 198 199 #define IC0_ASSIGNRD 0xB0400060 200 #define IC0_ASSIGNSET 0xB0400060 201 #define IC0_ASSIGNCLR 0xB0400064 202 203 #define IC0_WAKERD 0xB0400068 204 #define IC0_WAKESET 0xB0400068 205 #define IC0_WAKECLR 0xB040006C 206 207 #define IC0_MASKRD 0xB0400070 208 #define IC0_MASKSET 0xB0400070 209 #define IC0_MASKCLR 0xB0400074 210 211 #define IC0_RISINGRD 0xB0400078 212 #define IC0_RISINGCLR 0xB0400078 213 #define IC0_FALLINGRD 0xB040007C 214 #define IC0_FALLINGCLR 0xB040007C 215 216 #define IC0_TESTBIT 0xB0400080 217 218 /* Interrupt Controller 1 */ 219 #define IC1_CFG0RD 0xB1800040 220 #define IC1_CFG0SET 0xB1800040 221 #define IC1_CFG0CLR 0xB1800044 222 223 #define IC1_CFG1RD 0xB1800048 224 #define IC1_CFG1SET 0xB1800048 225 #define IC1_CFG1CLR 0xB180004C 226 227 #define IC1_CFG2RD 0xB1800050 228 #define IC1_CFG2SET 0xB1800050 229 #define IC1_CFG2CLR 0xB1800054 230 231 #define IC1_REQ0INT 0xB1800054 232 #define IC1_SRCRD 0xB1800058 233 #define IC1_SRCSET 0xB1800058 234 #define IC1_SRCCLR 0xB180005C 235 #define IC1_REQ1INT 0xB180005C 236 237 #define IC1_ASSIGNRD 0xB1800060 238 #define IC1_ASSIGNSET 0xB1800060 239 #define IC1_ASSIGNCLR 0xB1800064 240 241 #define IC1_WAKERD 0xB1800068 242 #define IC1_WAKESET 0xB1800068 243 #define IC1_WAKECLR 0xB180006C 244 245 #define IC1_MASKRD 0xB1800070 246 #define IC1_MASKSET 0xB1800070 247 #define IC1_MASKCLR 0xB1800074 248 249 #define IC1_RISINGRD 0xB1800078 250 #define IC1_RISINGCLR 0xB1800078 251 #define IC1_FALLINGRD 0xB180007C 252 #define IC1_FALLINGCLR 0xB180007C 253 254 #define IC1_TESTBIT 0xB1800080 255 256 /* Interrupt Configuration Modes */ 257 #define INTC_INT_DISABLED 0 258 #define INTC_INT_RISE_EDGE 0x1 259 #define INTC_INT_FALL_EDGE 0x2 260 #define INTC_INT_RISE_AND_FALL_EDGE 0x3 261 #define INTC_INT_HIGH_LEVEL 0x5 262 #define INTC_INT_LOW_LEVEL 0x6 263 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 264 265 /* Interrupt Numbers */ 266 #define AU1X00_UART0_INT 0 267 #define AU1000_UART1_INT 1 /* au1000 */ 268 #define AU1000_UART2_INT 2 /* au1000 */ 269 270 #define AU1500_PCI_INTA 1 /* au1500 */ 271 #define AU1500_PCI_INTB 2 /* au1500 */ 272 273 #define AU1X00_UART3_INT 3 274 275 #define AU1000_SSI0_INT 4 /* au1000 */ 276 #define AU1000_SSI1_INT 5 /* au1000 */ 277 278 #define AU1500_PCI_INTC 4 /* au1500 */ 279 #define AU1500_PCI_INTD 5 /* au1500 */ 280 281 #define AU1X00_DMA_INT_BASE 6 282 #define AU1X00_TOY_INT 14 283 #define AU1X00_TOY_MATCH0_INT 15 284 #define AU1X00_TOY_MATCH1_INT 16 285 #define AU1X00_TOY_MATCH2_INT 17 286 #define AU1X00_RTC_INT 18 287 #define AU1X00_RTC_MATCH0_INT 19 288 #define AU1X00_RTC_MATCH1_INT 20 289 #define AU1X00_RTC_MATCH2_INT 21 290 #define AU1000_IRDA_TX_INT 22 /* au1000 */ 291 #define AU1000_IRDA_RX_INT 23 /* au1000 */ 292 #define AU1X00_USB_DEV_REQ_INT 24 293 #define AU1X00_USB_DEV_SUS_INT 25 294 #define AU1X00_USB_HOST_INT 26 295 #define AU1X00_ACSYNC_INT 27 296 #define AU1X00_MAC0_DMA_INT 28 297 #define AU1X00_MAC1_DMA_INT 29 298 #define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT 299 #define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT 300 #define AU1000_I2S_UO_INT 30 /* au1000 */ 301 #define AU1X00_AC97C_INT 31 302 #define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT 303 #define AU1X00_GPIO_0 32 304 #define AU1X00_GPIO_1 33 305 #define AU1X00_GPIO_2 34 306 #define AU1X00_GPIO_3 35 307 #define AU1X00_GPIO_4 36 308 #define AU1X00_GPIO_5 37 309 #define AU1X00_GPIO_6 38 310 #define AU1X00_GPIO_7 39 311 #define AU1X00_GPIO_8 40 312 #define AU1X00_GPIO_9 41 313 #define AU1X00_GPIO_10 42 314 #define AU1X00_GPIO_11 43 315 #define AU1X00_GPIO_12 44 316 #define AU1X00_GPIO_13 45 317 #define AU1X00_GPIO_14 46 318 #define AU1X00_GPIO_15 47 319 320 /* Au1000 only */ 321 #define AU1000_GPIO_16 48 322 #define AU1000_GPIO_17 49 323 #define AU1000_GPIO_18 50 324 #define AU1000_GPIO_19 51 325 #define AU1000_GPIO_20 52 326 #define AU1000_GPIO_21 53 327 #define AU1000_GPIO_22 54 328 #define AU1000_GPIO_23 55 329 #define AU1000_GPIO_24 56 330 #define AU1000_GPIO_25 57 331 #define AU1000_GPIO_26 58 332 #define AU1000_GPIO_27 59 333 #define AU1000_GPIO_28 60 334 #define AU1000_GPIO_29 61 335 #define AU1000_GPIO_30 62 336 #define AU1000_GPIO_31 63 337 338 /* Au1500 only */ 339 #define AU1500_GPIO_200 48 340 #define AU1500_GPIO_201 49 341 #define AU1500_GPIO_202 50 342 #define AU1500_GPIO_203 51 343 #define AU1500_GPIO_20 52 344 #define AU1500_GPIO_204 53 345 #define AU1500_GPIO_205 54 346 #define AU1500_GPIO_23 55 347 #define AU1500_GPIO_24 56 348 #define AU1500_GPIO_25 57 349 #define AU1500_GPIO_26 58 350 #define AU1500_GPIO_27 59 351 #define AU1500_GPIO_28 60 352 #define AU1500_GPIO_206 61 353 #define AU1500_GPIO_207 62 354 #define AU1500_GPIO_208_215 63 355 356 #define AU1X00_MAX_INTR 63 357 358 #define AU1100_SD 2 359 #define AU1100_GPIO_208_215 29 360 /* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */ 361 362 /* Programmable Counters 0 and 1 */ 363 #define SYS_BASE 0xB1900000 364 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 365 #define SYS_CNTRL_E1S (1<<23) 366 #define SYS_CNTRL_T1S (1<<20) 367 #define SYS_CNTRL_M21 (1<<19) 368 #define SYS_CNTRL_M11 (1<<18) 369 #define SYS_CNTRL_M01 (1<<17) 370 #define SYS_CNTRL_C1S (1<<16) 371 #define SYS_CNTRL_BP (1<<14) 372 #define SYS_CNTRL_EN1 (1<<13) 373 #define SYS_CNTRL_BT1 (1<<12) 374 #define SYS_CNTRL_EN0 (1<<11) 375 #define SYS_CNTRL_BT0 (1<<10) 376 #define SYS_CNTRL_E0 (1<<8) 377 #define SYS_CNTRL_E0S (1<<7) 378 #define SYS_CNTRL_32S (1<<5) 379 #define SYS_CNTRL_T0S (1<<4) 380 #define SYS_CNTRL_M20 (1<<3) 381 #define SYS_CNTRL_M10 (1<<2) 382 #define SYS_CNTRL_M00 (1<<1) 383 #define SYS_CNTRL_C0S (1<<0) 384 385 /* Programmable Counter 0 Registers */ 386 #define SYS_TOYTRIM (SYS_BASE + 0) 387 #define SYS_TOYWRITE (SYS_BASE + 4) 388 #define SYS_TOYMATCH0 (SYS_BASE + 8) 389 #define SYS_TOYMATCH1 (SYS_BASE + 0xC) 390 #define SYS_TOYMATCH2 (SYS_BASE + 0x10) 391 #define SYS_TOYREAD (SYS_BASE + 0x40) 392 393 /* Programmable Counter 1 Registers */ 394 #define SYS_RTCTRIM (SYS_BASE + 0x44) 395 #define SYS_RTCWRITE (SYS_BASE + 0x48) 396 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 397 #define SYS_RTCMATCH1 (SYS_BASE + 0x50) 398 #define SYS_RTCMATCH2 (SYS_BASE + 0x54) 399 #define SYS_RTCREAD (SYS_BASE + 0x58) 400 401 /* I2S Controller */ 402 #define I2S_DATA 0xB1000000 403 #define I2S_DATA_MASK (0xffffff) 404 #define I2S_CONFIG 0xB1000004 405 #define I2S_CONFIG_XU (1<<25) 406 #define I2S_CONFIG_XO (1<<24) 407 #define I2S_CONFIG_RU (1<<23) 408 #define I2S_CONFIG_RO (1<<22) 409 #define I2S_CONFIG_TR (1<<21) 410 #define I2S_CONFIG_TE (1<<20) 411 #define I2S_CONFIG_TF (1<<19) 412 #define I2S_CONFIG_RR (1<<18) 413 #define I2S_CONFIG_RE (1<<17) 414 #define I2S_CONFIG_RF (1<<16) 415 #define I2S_CONFIG_PD (1<<11) 416 #define I2S_CONFIG_LB (1<<10) 417 #define I2S_CONFIG_IC (1<<9) 418 #define I2S_CONFIG_FM_BIT 7 419 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 420 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 421 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 422 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 423 #define I2S_CONFIG_TN (1<<6) 424 #define I2S_CONFIG_RN (1<<5) 425 #define I2S_CONFIG_SZ_BIT 0 426 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 427 428 #define I2S_CONTROL 0xB1000008 429 #define I2S_CONTROL_D (1<<1) 430 #define I2S_CONTROL_CE (1<<0) 431 432 /* USB Host Controller */ 433 /* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */ 434 #define USB_OHCI_BASE 0x10100000 435 #define USB_OHCI_LEN 0x00100000 436 #define USB_HOST_CONFIG 0xB017fffc 437 438 /* USB Device Controller */ 439 #define USBD_EP0RD 0xB0200000 440 #define USBD_EP0WR 0xB0200004 441 #define USBD_EP2WR 0xB0200008 442 #define USBD_EP3WR 0xB020000C 443 #define USBD_EP4RD 0xB0200010 444 #define USBD_EP5RD 0xB0200014 445 #define USBD_INTEN 0xB0200018 446 #define USBD_INTSTAT 0xB020001C 447 #define USBDEV_INT_SOF (1<<12) 448 #define USBDEV_INT_HF_BIT 6 449 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 450 #define USBDEV_INT_CMPLT_BIT 0 451 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 452 #define USBD_CONFIG 0xB0200020 453 #define USBD_EP0CS 0xB0200024 454 #define USBD_EP2CS 0xB0200028 455 #define USBD_EP3CS 0xB020002C 456 #define USBD_EP4CS 0xB0200030 457 #define USBD_EP5CS 0xB0200034 458 #define USBDEV_CS_SU (1<<14) 459 #define USBDEV_CS_NAK (1<<13) 460 #define USBDEV_CS_ACK (1<<12) 461 #define USBDEV_CS_BUSY (1<<11) 462 #define USBDEV_CS_TSIZE_BIT 1 463 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 464 #define USBDEV_CS_STALL (1<<0) 465 #define USBD_EP0RDSTAT 0xB0200040 466 #define USBD_EP0WRSTAT 0xB0200044 467 #define USBD_EP2WRSTAT 0xB0200048 468 #define USBD_EP3WRSTAT 0xB020004C 469 #define USBD_EP4RDSTAT 0xB0200050 470 #define USBD_EP5RDSTAT 0xB0200054 471 #define USBDEV_FSTAT_FLUSH (1<<6) 472 #define USBDEV_FSTAT_UF (1<<5) 473 #define USBDEV_FSTAT_OF (1<<4) 474 #define USBDEV_FSTAT_FCNT_BIT 0 475 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 476 #define USBD_ENABLE 0xB0200058 477 #define USBDEV_ENABLE (1<<1) 478 #define USBDEV_CE (1<<0) 479 480 /* Ethernet Controllers */ 481 #define AU1000_ETH0_BASE 0xB0500000 482 #define AU1000_ETH1_BASE 0xB0510000 483 #define AU1500_ETH0_BASE 0xB1500000 484 #define AU1500_ETH1_BASE 0xB1510000 485 #define AU1100_ETH0_BASE 0xB0500000 486 #define AU1550_ETH0_BASE 0xB0500000 487 #define AU1550_ETH1_BASE 0xB0510000 488 489 /* 4 byte offsets from AU1000_ETH_BASE */ 490 #define MAC_CONTROL 0x0 491 #define MAC_RX_ENABLE (1<<2) 492 #define MAC_TX_ENABLE (1<<3) 493 #define MAC_DEF_CHECK (1<<5) 494 #define MAC_SET_BL(X) (((X)&0x3)<<6) 495 #define MAC_AUTO_PAD (1<<8) 496 #define MAC_DISABLE_RETRY (1<<10) 497 #define MAC_DISABLE_BCAST (1<<11) 498 #define MAC_LATE_COL (1<<12) 499 #define MAC_HASH_MODE (1<<13) 500 #define MAC_HASH_ONLY (1<<15) 501 #define MAC_PASS_ALL (1<<16) 502 #define MAC_INVERSE_FILTER (1<<17) 503 #define MAC_PROMISCUOUS (1<<18) 504 #define MAC_PASS_ALL_MULTI (1<<19) 505 #define MAC_FULL_DUPLEX (1<<20) 506 #define MAC_NORMAL_MODE 0 507 #define MAC_INT_LOOPBACK (1<<21) 508 #define MAC_EXT_LOOPBACK (1<<22) 509 #define MAC_DISABLE_RX_OWN (1<<23) 510 #define MAC_BIG_ENDIAN (1<<30) 511 #define MAC_RX_ALL (1<<31) 512 #define MAC_ADDRESS_HIGH 0x4 513 #define MAC_ADDRESS_LOW 0x8 514 #define MAC_MCAST_HIGH 0xC 515 #define MAC_MCAST_LOW 0x10 516 #define MAC_MII_CNTRL 0x14 517 #define MAC_MII_BUSY (1<<0) 518 #define MAC_MII_READ 0 519 #define MAC_MII_WRITE (1<<1) 520 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 521 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 522 #define MAC_MII_DATA 0x18 523 #define MAC_FLOW_CNTRL 0x1C 524 #define MAC_FLOW_CNTRL_BUSY (1<<0) 525 #define MAC_FLOW_CNTRL_ENABLE (1<<1) 526 #define MAC_PASS_CONTROL (1<<2) 527 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 528 #define MAC_VLAN1_TAG 0x20 529 #define MAC_VLAN2_TAG 0x24 530 531 /* Ethernet Controller Enable */ 532 #define AU1000_MAC0_ENABLE 0xB0520000 533 #define AU1000_MAC1_ENABLE 0xB0520004 534 #define AU1500_MAC0_ENABLE 0xB1520000 535 #define AU1500_MAC1_ENABLE 0xB1520004 536 #define AU1100_MAC0_ENABLE 0xB0520000 537 #define AU1550_MAC0_ENABLE 0xB0520000 538 #define AU1550_MAC1_ENABLE 0xB0520004 539 540 #define MAC_EN_CLOCK_ENABLE (1<<0) 541 #define MAC_EN_RESET0 (1<<1) 542 #define MAC_EN_TOSS (0<<2) 543 #define MAC_EN_CACHEABLE (1<<3) 544 #define MAC_EN_RESET1 (1<<4) 545 #define MAC_EN_RESET2 (1<<5) 546 #define MAC_DMA_RESET (1<<6) 547 548 /* Ethernet Controller DMA Channels */ 549 550 #define MAC0_TX_DMA_ADDR 0xB4004000 551 #define MAC1_TX_DMA_ADDR 0xB4004200 552 /* offsets from MAC_TX_RING_ADDR address */ 553 #define MAC_TX_BUFF0_STATUS 0x0 554 #define TX_FRAME_ABORTED (1<<0) 555 #define TX_JAB_TIMEOUT (1<<1) 556 #define TX_NO_CARRIER (1<<2) 557 #define TX_LOSS_CARRIER (1<<3) 558 #define TX_EXC_DEF (1<<4) 559 #define TX_LATE_COLL_ABORT (1<<5) 560 #define TX_EXC_COLL (1<<6) 561 #define TX_UNDERRUN (1<<7) 562 #define TX_DEFERRED (1<<8) 563 #define TX_LATE_COLL (1<<9) 564 #define TX_COLL_CNT_MASK (0xF<<10) 565 #define TX_PKT_RETRY (1<<31) 566 #define MAC_TX_BUFF0_ADDR 0x4 567 #define TX_DMA_ENABLE (1<<0) 568 #define TX_T_DONE (1<<1) 569 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 570 #define MAC_TX_BUFF0_LEN 0x8 571 #define MAC_TX_BUFF1_STATUS 0x10 572 #define MAC_TX_BUFF1_ADDR 0x14 573 #define MAC_TX_BUFF1_LEN 0x18 574 #define MAC_TX_BUFF2_STATUS 0x20 575 #define MAC_TX_BUFF2_ADDR 0x24 576 #define MAC_TX_BUFF2_LEN 0x28 577 #define MAC_TX_BUFF3_STATUS 0x30 578 #define MAC_TX_BUFF3_ADDR 0x34 579 #define MAC_TX_BUFF3_LEN 0x38 580 581 #define MAC0_RX_DMA_ADDR 0xB4004100 582 #define MAC1_RX_DMA_ADDR 0xB4004300 583 /* offsets from MAC_RX_RING_ADDR */ 584 #define MAC_RX_BUFF0_STATUS 0x0 585 #define RX_FRAME_LEN_MASK 0x3fff 586 #define RX_WDOG_TIMER (1<<14) 587 #define RX_RUNT (1<<15) 588 #define RX_OVERLEN (1<<16) 589 #define RX_COLL (1<<17) 590 #define RX_ETHER (1<<18) 591 #define RX_MII_ERROR (1<<19) 592 #define RX_DRIBBLING (1<<20) 593 #define RX_CRC_ERROR (1<<21) 594 #define RX_VLAN1 (1<<22) 595 #define RX_VLAN2 (1<<23) 596 #define RX_LEN_ERROR (1<<24) 597 #define RX_CNTRL_FRAME (1<<25) 598 #define RX_U_CNTRL_FRAME (1<<26) 599 #define RX_MCAST_FRAME (1<<27) 600 #define RX_BCAST_FRAME (1<<28) 601 #define RX_FILTER_FAIL (1<<29) 602 #define RX_PACKET_FILTER (1<<30) 603 #define RX_MISSED_FRAME (1<<31) 604 605 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 606 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 607 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 608 #define MAC_RX_BUFF0_ADDR 0x4 609 #define RX_DMA_ENABLE (1<<0) 610 #define RX_T_DONE (1<<1) 611 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 612 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 613 #define MAC_RX_BUFF1_STATUS 0x10 614 #define MAC_RX_BUFF1_ADDR 0x14 615 #define MAC_RX_BUFF2_STATUS 0x20 616 #define MAC_RX_BUFF2_ADDR 0x24 617 #define MAC_RX_BUFF3_STATUS 0x30 618 #define MAC_RX_BUFF3_ADDR 0x34 619 620 621 /* UARTS 0-3 */ 622 #define UART0_ADDR 0xB1100000 623 #define UART1_ADDR 0xB1200000 624 #define UART2_ADDR 0xB1300000 625 #define UART3_ADDR 0xB1400000 626 #define UART_BASE UART0_ADDR 627 #define UART_DEBUG_BASE UART2_ADDR 628 629 #define UART_RX 0 /* Receive buffer */ 630 #define UART_TX 4 /* Transmit buffer */ 631 #define UART_IER 8 /* Interrupt Enable Register */ 632 #define UART_IIR 0xC /* Interrupt ID Register */ 633 #define UART_FCR 0x10 /* FIFO Control Register */ 634 #define UART_LCR 0x14 /* Line Control Register */ 635 #define UART_MCR 0x18 /* Modem Control Register */ 636 #define UART_LSR 0x1C /* Line Status Register */ 637 #define UART_MSR 0x20 /* Modem Status Register */ 638 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ 639 #define UART_ENABLE 0x100 /* Uart enable */ 640 641 #define UART_EN_CE 1 /* Clock enable */ 642 #define UART_EN_E 2 /* Enable */ 643 644 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 645 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 646 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 647 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 648 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ 649 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ 650 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ 651 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ 652 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ 653 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ 654 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ 655 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ 656 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ 657 658 /* 659 * These are the definitions for the Line Control Register 660 */ 661 #define UART_LCR_SBC 0x40 /* Set break control */ 662 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 663 #define UART_LCR_EPAR 0x10 /* Even parity select */ 664 #define UART_LCR_PARITY 0x08 /* Parity Enable */ 665 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 666 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 667 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 668 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 669 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 670 671 /* 672 * These are the definitions for the Line Status Register 673 */ 674 #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 675 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 676 #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 677 #define UART_LSR_FE 0x08 /* Frame error indicator */ 678 #define UART_LSR_PE 0x04 /* Parity error indicator */ 679 #define UART_LSR_OE 0x02 /* Overrun error indicator */ 680 #define UART_LSR_DR 0x01 /* Receiver data ready */ 681 682 /* 683 * These are the definitions for the Interrupt Identification Register 684 */ 685 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 686 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 687 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 688 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 689 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 690 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 691 692 /* 693 * These are the definitions for the Interrupt Enable Register 694 */ 695 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 696 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 697 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 698 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 699 700 /* 701 * These are the definitions for the Modem Control Register 702 */ 703 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 704 #define UART_MCR_OUT2 0x08 /* Out2 complement */ 705 #define UART_MCR_OUT1 0x04 /* Out1 complement */ 706 #define UART_MCR_RTS 0x02 /* RTS complement */ 707 #define UART_MCR_DTR 0x01 /* DTR complement */ 708 709 /* 710 * These are the definitions for the Modem Status Register 711 */ 712 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 713 #define UART_MSR_RI 0x40 /* Ring Indicator */ 714 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 715 #define UART_MSR_CTS 0x10 /* Clear to Send */ 716 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 717 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 718 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 719 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 720 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 721 722 723 /* SSIO */ 724 #define SSI0_STATUS 0xB1600000 725 #define SSI_STATUS_BF (1<<4) 726 #define SSI_STATUS_OF (1<<3) 727 #define SSI_STATUS_UF (1<<2) 728 #define SSI_STATUS_D (1<<1) 729 #define SSI_STATUS_B (1<<0) 730 #define SSI0_INT 0xB1600004 731 #define SSI_INT_OI (1<<3) 732 #define SSI_INT_UI (1<<2) 733 #define SSI_INT_DI (1<<1) 734 #define SSI0_INT_ENABLE 0xB1600008 735 #define SSI_INTE_OIE (1<<3) 736 #define SSI_INTE_UIE (1<<2) 737 #define SSI_INTE_DIE (1<<1) 738 #define SSI0_CONFIG 0xB1600020 739 #define SSI_CONFIG_AO (1<<24) 740 #define SSI_CONFIG_DO (1<<23) 741 #define SSI_CONFIG_ALEN_BIT 20 742 #define SSI_CONFIG_ALEN_MASK (0x7<<20) 743 #define SSI_CONFIG_DLEN_BIT 16 744 #define SSI_CONFIG_DLEN_MASK (0x7<<16) 745 #define SSI_CONFIG_DD (1<<11) 746 #define SSI_CONFIG_AD (1<<10) 747 #define SSI_CONFIG_BM_BIT 8 748 #define SSI_CONFIG_BM_MASK (0x3<<8) 749 #define SSI_CONFIG_CE (1<<7) 750 #define SSI_CONFIG_DP (1<<6) 751 #define SSI_CONFIG_DL (1<<5) 752 #define SSI_CONFIG_EP (1<<4) 753 #define SSI0_ADATA 0xB1600024 754 #define SSI_AD_D (1<<24) 755 #define SSI_AD_ADDR_BIT 16 756 #define SSI_AD_ADDR_MASK (0xff<<16) 757 #define SSI_AD_DATA_BIT 0 758 #define SSI_AD_DATA_MASK (0xfff<<0) 759 #define SSI0_CLKDIV 0xB1600028 760 #define SSI0_CONTROL 0xB1600100 761 #define SSI_CONTROL_CD (1<<1) 762 #define SSI_CONTROL_E (1<<0) 763 764 /* SSI1 */ 765 #define SSI1_STATUS 0xB1680000 766 #define SSI1_INT 0xB1680004 767 #define SSI1_INT_ENABLE 0xB1680008 768 #define SSI1_CONFIG 0xB1680020 769 #define SSI1_ADATA 0xB1680024 770 #define SSI1_CLKDIV 0xB1680028 771 #define SSI1_ENABLE 0xB1680100 772 773 /* 774 * Register content definitions 775 */ 776 #define SSI_STATUS_BF (1<<4) 777 #define SSI_STATUS_OF (1<<3) 778 #define SSI_STATUS_UF (1<<2) 779 #define SSI_STATUS_D (1<<1) 780 #define SSI_STATUS_B (1<<0) 781 782 /* SSI_INT */ 783 #define SSI_INT_OI (1<<3) 784 #define SSI_INT_UI (1<<2) 785 #define SSI_INT_DI (1<<1) 786 787 /* SSI_INTEN */ 788 #define SSI_INTEN_OIE (1<<3) 789 #define SSI_INTEN_UIE (1<<2) 790 #define SSI_INTEN_DIE (1<<1) 791 792 #define SSI_CONFIG_AO (1<<24) 793 #define SSI_CONFIG_DO (1<<23) 794 #define SSI_CONFIG_ALEN (7<<20) 795 #define SSI_CONFIG_DLEN (15<<16) 796 #define SSI_CONFIG_DD (1<<11) 797 #define SSI_CONFIG_AD (1<<10) 798 #define SSI_CONFIG_BM (3<<8) 799 #define SSI_CONFIG_CE (1<<7) 800 #define SSI_CONFIG_DP (1<<6) 801 #define SSI_CONFIG_DL (1<<5) 802 #define SSI_CONFIG_EP (1<<4) 803 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) 804 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) 805 #define SSI_CONFIG_BM_HI (0<<8) 806 #define SSI_CONFIG_BM_LO (1<<8) 807 #define SSI_CONFIG_BM_CY (2<<8) 808 809 #define SSI_ADATA_D (1<<24) 810 #define SSI_ADATA_ADDR (0xFF<<16) 811 #define SSI_ADATA_DATA (0x0FFF) 812 #define SSI_ADATA_ADDR_N(N) (N<<16) 813 814 #define SSI_ENABLE_CD (1<<1) 815 #define SSI_ENABLE_E (1<<0) 816 817 818 /* IrDA Controller */ 819 #define IRDA_BASE 0xB0300000 820 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00) 821 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) 822 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) 823 #define IR_RING_SIZE (IRDA_BASE+0x0C) 824 #define IR_RING_PROMPT (IRDA_BASE+0x10) 825 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 826 #define IR_INT_CLEAR (IRDA_BASE+0x18) 827 #define IR_CONFIG_1 (IRDA_BASE+0x20) 828 #define IR_RX_INVERT_LED (1<<0) 829 #define IR_TX_INVERT_LED (1<<1) 830 #define IR_ST (1<<2) 831 #define IR_SF (1<<3) 832 #define IR_SIR (1<<4) 833 #define IR_MIR (1<<5) 834 #define IR_FIR (1<<6) 835 #define IR_16CRC (1<<7) 836 #define IR_TD (1<<8) 837 #define IR_RX_ALL (1<<9) 838 #define IR_DMA_ENABLE (1<<10) 839 #define IR_RX_ENABLE (1<<11) 840 #define IR_TX_ENABLE (1<<12) 841 #define IR_LOOPBACK (1<<14) 842 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 843 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 844 #define IR_SIR_FLAGS (IRDA_BASE+0x24) 845 #define IR_ENABLE (IRDA_BASE+0x28) 846 #define IR_RX_STATUS (1<<9) 847 #define IR_TX_STATUS (1<<10) 848 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 849 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 850 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 851 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 852 #define IR_CONFIG_2 (IRDA_BASE+0x3C) 853 #define IR_MODE_INV (1<<0) 854 #define IR_ONE_PIN (1<<1) 855 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 856 857 /* GPIO */ 858 #define SYS_PINFUNC 0xB190002C 859 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 860 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 861 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 862 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 863 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 864 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 865 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 866 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 867 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 868 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 869 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 870 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 871 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 872 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 873 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 874 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 875 #define SYS_TRIOUTRD 0xB1900100 876 #define SYS_TRIOUTCLR 0xB1900100 877 #define SYS_OUTPUTRD 0xB1900108 878 #define SYS_OUTPUTSET 0xB1900108 879 #define SYS_OUTPUTCLR 0xB190010C 880 #define SYS_PINSTATERD 0xB1900110 881 #define SYS_PININPUTEN 0xB1900110 882 883 /* GPIO2, Au1500 only */ 884 #define GPIO2_BASE 0xB1700000 885 #define GPIO2_DIR (GPIO2_BASE + 0) 886 #define GPIO2_DATA_EN (GPIO2_BASE + 8) 887 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) 888 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10) 889 #define GPIO2_ENABLE (GPIO2_BASE + 0x14) 890 891 /* Power Management */ 892 #define SYS_SCRATCH0 0xB1900018 893 #define SYS_SCRATCH1 0xB190001C 894 #define SYS_WAKEMSK 0xB1900034 895 #define SYS_ENDIAN 0xB1900038 896 #define SYS_POWERCTRL 0xB190003C 897 #define SYS_WAKESRC 0xB190005C 898 #define SYS_SLPPWR 0xB1900078 899 #define SYS_SLEEP 0xB190007C 900 901 /* Clock Controller */ 902 #define SYS_FREQCTRL0 0xB1900020 903 #define SYS_FC_FRDIV2_BIT 22 904 #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) 905 #define SYS_FC_FE2 (1<<21) 906 #define SYS_FC_FS2 (1<<20) 907 #define SYS_FC_FRDIV1_BIT 12 908 #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) 909 #define SYS_FC_FE1 (1<<11) 910 #define SYS_FC_FS1 (1<<10) 911 #define SYS_FC_FRDIV0_BIT 2 912 #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) 913 #define SYS_FC_FE0 (1<<1) 914 #define SYS_FC_FS0 (1<<0) 915 #define SYS_FREQCTRL1 0xB1900024 916 #define SYS_FC_FRDIV5_BIT 22 917 #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) 918 #define SYS_FC_FE5 (1<<21) 919 #define SYS_FC_FS5 (1<<20) 920 #define SYS_FC_FRDIV4_BIT 12 921 #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) 922 #define SYS_FC_FE4 (1<<11) 923 #define SYS_FC_FS4 (1<<10) 924 #define SYS_FC_FRDIV3_BIT 2 925 #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) 926 #define SYS_FC_FE3 (1<<1) 927 #define SYS_FC_FS3 (1<<0) 928 #define SYS_CLKSRC 0xB1900028 929 #define SYS_CS_ME1_BIT 27 930 #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT) 931 #define SYS_CS_DE1 (1<<26) 932 #define SYS_CS_CE1 (1<<25) 933 #define SYS_CS_ME0_BIT 22 934 #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT) 935 #define SYS_CS_DE0 (1<<21) 936 #define SYS_CS_CE0 (1<<20) 937 #define SYS_CS_MI2_BIT 17 938 #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT) 939 #define SYS_CS_DI2 (1<<16) 940 #define SYS_CS_CI2 (1<<15) 941 #define SYS_CS_MUH_BIT 12 942 #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT) 943 #define SYS_CS_DUH (1<<11) 944 #define SYS_CS_CUH (1<<10) 945 #define SYS_CS_MUD_BIT 7 946 #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT) 947 #define SYS_CS_DUD (1<<6) 948 #define SYS_CS_CUD (1<<5) 949 #define SYS_CS_MIR_BIT 2 950 #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT) 951 #define SYS_CS_DIR (1<<1) 952 #define SYS_CS_CIR (1<<0) 953 954 #define SYS_CS_MUX_AUX 0x1 955 #define SYS_CS_MUX_FQ0 0x2 956 #define SYS_CS_MUX_FQ1 0x3 957 #define SYS_CS_MUX_FQ2 0x4 958 #define SYS_CS_MUX_FQ3 0x5 959 #define SYS_CS_MUX_FQ4 0x6 960 #define SYS_CS_MUX_FQ5 0x7 961 #define SYS_CPUPLL 0xB1900060 962 #define SYS_AUXPLL 0xB1900064 963 964 /* AC97 Controller */ 965 #define AC97C_CONFIG 0xB0000000 966 #define AC97C_RECV_SLOTS_BIT 13 967 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 968 #define AC97C_XMIT_SLOTS_BIT 3 969 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 970 #define AC97C_SG (1<<2) 971 #define AC97C_SYNC (1<<1) 972 #define AC97C_RESET (1<<0) 973 #define AC97C_STATUS 0xB0000004 974 #define AC97C_XU (1<<11) 975 #define AC97C_XO (1<<10) 976 #define AC97C_RU (1<<9) 977 #define AC97C_RO (1<<8) 978 #define AC97C_READY (1<<7) 979 #define AC97C_CP (1<<6) 980 #define AC97C_TR (1<<5) 981 #define AC97C_TE (1<<4) 982 #define AC97C_TF (1<<3) 983 #define AC97C_RR (1<<2) 984 #define AC97C_RE (1<<1) 985 #define AC97C_RF (1<<0) 986 #define AC97C_DATA 0xB0000008 987 #define AC97C_CMD 0xB000000C 988 #define AC97C_WD_BIT 16 989 #define AC97C_READ (1<<7) 990 #define AC97C_INDEX_MASK 0x7f 991 #define AC97C_CNTRL 0xB0000010 992 #define AC97C_RS (1<<1) 993 #define AC97C_CE (1<<0) 994 995 #define DB1000_BCSR_ADDR 0xAE000000 996 #define DB1550_BCSR_ADDR 0xAF000000 997 998 #ifdef CONFIG_DBAU1550 999 #define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR 1000 #else 1001 #define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR 1002 #endif 1003 1004 #ifdef CONFIG_SOC_AU1500 1005 /* Au1500 PCI Controller */ 1006 #define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */ 1007 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1008 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1009 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1010 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1011 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1012 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1013 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 1014 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 1015 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 1016 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 1017 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 1018 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 1019 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 1020 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 1021 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 1022 1023 #define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */ 1024 1025 /* All of our structures, like pci resource, have 32 bit members. 1026 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 1027 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch 1028 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 1029 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM 1030 * addresses. For PCI IO, it's simpler because we get to do the ioremap 1031 * ourselves and then adjust the device's resources. 1032 */ 1033 #define Au1500_EXT_CFG 0x600000000 1034 #define Au1500_EXT_CFG_TYPE1 0x680000000 1035 #define Au1500_PCI_IO_START 0x500000000 1036 #define Au1500_PCI_IO_END 0x5000FFFFF 1037 #define Au1500_PCI_MEM_START 0x440000000 1038 #define Au1500_PCI_MEM_END 0x443FFFFFF 1039 1040 #define PCI_IO_START (Au1500_PCI_IO_START + 0x300) 1041 #define PCI_IO_END (Au1500_PCI_IO_END) 1042 #define PCI_MEM_START (Au1500_PCI_MEM_START) 1043 #define PCI_MEM_END (Au1500_PCI_MEM_END) 1044 #define PCI_FIRST_DEVFN (0<<3) 1045 #define PCI_LAST_DEVFN (19<<3) 1046 1047 #endif 1048 1049 #if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000)) 1050 /* no PCI bus controller */ 1051 #define PCI_IO_START 0 1052 #define PCI_IO_END 0 1053 #define PCI_MEM_START 0 1054 #define PCI_MEM_END 0 1055 #define PCI_FIRST_DEVFN 0 1056 #define PCI_LAST_DEVFN 0 1057 #endif 1058 #define AU1X_SOCK0_IO 0xF00000000 1059 #define AU1X_SOCK0_PHYS_ATTR 0xF40000000 1060 #define AU1X_SOCK0_PHYS_MEM 0xF80000000 1061 1062 /* pcmcia socket 1 needs external glue logic so the memory map 1063 * differs from board to board. 1064 */ 1065 1066 /* Only for db board, not older pb */ 1067 #define AU1X_SOCK1_IO 0xF04000000 1068 #define AU1X_SOCK1_PHYS_ATTR 0xF44000000 1069 #define AU1X_SOCK1_PHYS_MEM 0xF84000000 1070 1071 #endif 1072
