/external/llvm/lib/Target/Lanai/ |
LanaiISelLowering.cpp | 73 setOperationAction(ISD::SETCC, MVT::i32, Custom); 178 case ISD::SETCC: [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiISelLowering.cpp | 89 setOperationAction(ISD::SETCC, MVT::i32, Custom); 193 case ISD::SETCC: [all...] |
/external/v8/src/ia32/ |
disasm-ia32.cc | 387 int SetCC(byte* data); 712 int DisassemblerIA32::SetCC(byte* data) { [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SETCC); 175 setOperationAction(ISD::SETCC, MVT::i32, Legal); 179 setOperationAction(ISD::SETCC, MVT::f32, Legal); 184 setOperationAction(ISD::SETCC, MVT::f64, Legal); 222 setOperationAction(ISD::SETCC, MVT::i64, Legal); 285 setOperationAction(ISD::SETCC, Ty, Legal); 322 setOperationAction(ISD::SETCC, Ty, Legal); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 105 setTargetDAGCombine(ISD::SETCC); 128 setOperationAction(ISD::SETCC, MVT::f16, Promote); 242 setOperationAction(ISD::SETCC, MVT::i32, Legal); 246 setOperationAction(ISD::SETCC, MVT::f32, Legal); 251 setOperationAction(ISD::SETCC, MVT::f64, Legal); 289 setOperationAction(ISD::SETCC, MVT::i64, Legal); 356 setOperationAction(ISD::SETCC, Ty, Legal); 393 setOperationAction(ISD::SETCC, Ty, Legal); [all...] |
/external/v8/src/x64/ |
disasm-x64.cc | 472 int SetCC(byte* data); 870 int DisassemblerX64::SetCC(byte* data) { [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 111 setOperationAction(ISD::SETCC, MVT::i1, Promote); 112 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); 113 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); 229 setTargetDAGCombine(ISD::SETCC); 541 // create setcc with i1 operands. We don't have instructions for i1 setcc. 542 if (VT == MVT::i1 && Op == ISD::SETCC) [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 69 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 518 // Get the SETCC result using the canonical SETCC type. 519 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), 524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 774 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break [all...] |
DAGCombiner.cpp | 495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 496 // that selects between the values 1 and 0, making it equivalent to a setcc. 502 if (N.getOpcode() == ISD::SETCC) { 521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only [all...] |
/external/v8/src/arm/ |
constants-arm.h | 223 SetCC = 1 << 20, // Set condition code.
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 578 // Promote all the way up to the canonical SetCC type. 619 // Get the SETCC result using the canonical SETCC type. 620 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS, 625 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); [all...] |
DAGCombiner.cpp | 729 // Return true if this node is a setcc, or is a select_cc 731 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to 736 if (N.getOpcode() == ISD::SETCC) { 758 /// Return true if this is a SetCC-equivalent operation with only one use. [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 79 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 613 // Get the SETCC result using the canonical SETCC type. 614 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), 618 return DAG.getSExtOrTrunc(SetCC, dl, NVT); [all...] |
DAGCombiner.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 135 setOperationAction(ISD::SETCC, VT, Custom); 363 setOperationAction(ISD::SETCC, VT, Custom); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 63 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so 108 setOperationAction(ISD::SETCC, MVT::i32, Custom); 109 setOperationAction(ISD::SETCC, MVT::i64, Custom); 110 setOperationAction(ISD::SETCC, MVT::f32, Custom); 111 setOperationAction(ISD::SETCC, MVT::f64, Custom); 159 setOperationAction(ISD::SETCC, MVT::f128, Custom); 262 setOperationAction(ISD::SETCC, MVT::f16, Promote); 332 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); 365 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); 543 setOperationAction(ISD::SETCC, MVT::v1f64, Expand) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86ISelLowering.cpp | 182 // X86 is weird, it always uses i8 for shift amounts and setcc results. 424 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 425 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 426 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 427 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 428 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 429 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 432 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 122 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so 167 setOperationAction(ISD::SETCC, MVT::i32, Custom); 168 setOperationAction(ISD::SETCC, MVT::i64, Custom); 169 setOperationAction(ISD::SETCC, MVT::f16, Custom); 170 setOperationAction(ISD::SETCC, MVT::f32, Custom); 171 setOperationAction(ISD::SETCC, MVT::f64, Custom); 226 setOperationAction(ISD::SETCC, MVT::f128, Custom); 370 setOperationAction(ISD::SETCC, MVT::f16, Promote); 409 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); 436 setOperationAction(ISD::SETCC, MVT::v8f16, Expand) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 191 setOperationAction(ISD::SETCC, MVT::i1, Promote); 192 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); 193 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); 194 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 631 setTargetDAGCombine(ISD::SETCC); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 82 // X86 is weird. It always uses i8 for shift amounts and setcc results. 390 setOperationAction(ISD::SETCC, VT, Custom); 396 setOperationAction(ISD::SETCC, VT, Custom); 681 setOperationAction(ISD::SETCC, VT, Expand); [all...] |