/external/llvm/lib/CodeGen/ |
RegisterCoalescer.h | 42 unsigned SrcIdx; 61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 109 unsigned getSrcIdx() const { return SrcIdx; }
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PeepholeOptimizer.cpp | [all...] |
TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx, [all...] |
RegisterCoalescer.cpp | 315 SrcIdx = DstIdx = 0; 362 SrcIdx, DstIdx); 367 SrcIdx = DstSub; 384 if (DstIdx && !SrcIdx) { 386 std::swap(SrcIdx, DstIdx); 405 std::swap(SrcIdx, DstIdx); 429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); 443 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
RegisterCoalescer.h | 41 unsigned SrcIdx = 0; 105 unsigned getSrcIdx() const { return SrcIdx; }
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PeepholeOptimizer.cpp | [all...] |
TwoAddressInstructionPass.cpp | 157 unsigned SrcIdx, unsigned DstIdx, [all...] |
RegisterCoalescer.cpp | 349 SrcIdx = DstIdx = 0; 396 SrcIdx, DstIdx); 401 SrcIdx = DstSub; 418 if (DstIdx && !SrcIdx) { 420 std::swap(SrcIdx, DstIdx); 439 std::swap(SrcIdx, DstIdx); 463 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); 477 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == [all...] |
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
InstCombineVectorOps.cpp | 215 int SrcIdx = getShuffleMask(SVI)[Elt->getZExtValue()]; 220 if (SrcIdx < 0) 222 if (SrcIdx < (int)LHSWidth) 225 SrcIdx -= LHSWidth; 231 SrcIdx, false));
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
InferAddressSpaces.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86MCInstLower.cpp | [all...] |
X86InstrInfo.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineVectorOps.cpp | 229 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue()); 234 if (SrcIdx < 0) 236 if (SrcIdx < (int)LHSWidth) 239 SrcIdx -= LHSWidth; 245 SrcIdx, false)); [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
TwoAddressInstructionPass.cpp | 126 unsigned SrcIdx, unsigned DstIdx, 864 unsigned SrcIdx, unsigned DstIdx, unsigned Dist [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
R600InstrInfo.cpp | 256 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { 272 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { 317 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); 318 if (SrcIdx < 0) 320 MachineOperand &MO = MI.getOperand(SrcIdx); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86MCInstLower.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/ |
InstCombineVectorOps.cpp | 255 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue()); 260 if (SrcIdx < 0) 262 if (SrcIdx < (int)LHSWidth) 265 SrcIdx -= LHSWidth; 271 SrcIdx, false)); [all...] |
InstCombineCalls.cpp | 534 unsigned SrcIdx = Lane * NumSrcEltsPerLane + Elt % NumSrcEltsPerLane; 536 auto *COp = Cst->getAggregateElement(SrcIdx); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
AMDGPUAsmParser.cpp | [all...] |