1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek (at) xilinx.com> 5 */ 6 7 #ifndef _ASM_ARCH_SYS_PROTO_H 8 #define _ASM_ARCH_SYS_PROTO_H 9 10 #define PAYLOAD_ARG_CNT 5 11 12 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF 13 #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D 14 #define KEY_PTR_LEN 32 15 16 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 17 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2 18 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 19 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 20 #define ZYNQMP_FPGA_BIT_NS 5 21 22 #define ZYNQMP_FPGA_AUTH_DDR 1 23 24 enum { 25 IDCODE, 26 VERSION, 27 IDCODE2, 28 }; 29 30 enum { 31 ZYNQMP_SILICON_V1, 32 ZYNQMP_SILICON_V2, 33 ZYNQMP_SILICON_V3, 34 ZYNQMP_SILICON_V4, 35 }; 36 37 enum { 38 TCM_LOCK, 39 TCM_SPLIT, 40 }; 41 42 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); 43 unsigned int zynqmp_get_silicon_version(void); 44 45 void handoff_setup(void); 46 47 void zynqmp_pmufw_version(void); 48 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); 49 int zynqmp_mmio_read(const u32 address, u32 *value); 50 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, 51 u32 *ret_payload); 52 53 void initialize_tcm(bool mode); 54 void mem_map_fill(void); 55 int chip_id(unsigned char id); 56 57 #endif /* _ASM_ARCH_SYS_PROTO_H */ 58
