1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef _TEGRA210_PINMUX_H_ 7 #define _TEGRA210_PINMUX_H_ 8 9 enum pmux_pingrp { 10 PMUX_PINGRP_SDMMC1_CLK_PM0, 11 PMUX_PINGRP_SDMMC1_CMD_PM1, 12 PMUX_PINGRP_SDMMC1_DAT3_PM2, 13 PMUX_PINGRP_SDMMC1_DAT2_PM3, 14 PMUX_PINGRP_SDMMC1_DAT1_PM4, 15 PMUX_PINGRP_SDMMC1_DAT0_PM5, 16 PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4), 17 PMUX_PINGRP_SDMMC3_CMD_PP1, 18 PMUX_PINGRP_SDMMC3_DAT0_PP5, 19 PMUX_PINGRP_SDMMC3_DAT1_PP4, 20 PMUX_PINGRP_SDMMC3_DAT2_PP3, 21 PMUX_PINGRP_SDMMC3_DAT3_PP2, 22 PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4), 23 PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1, 24 PMUX_PINGRP_PEX_WAKE_N_PA2, 25 PMUX_PINGRP_PEX_L1_RST_N_PA3, 26 PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4, 27 PMUX_PINGRP_SATA_LED_ACTIVE_PA5, 28 PMUX_PINGRP_SPI1_MOSI_PC0, 29 PMUX_PINGRP_SPI1_MISO_PC1, 30 PMUX_PINGRP_SPI1_SCK_PC2, 31 PMUX_PINGRP_SPI1_CS0_PC3, 32 PMUX_PINGRP_SPI1_CS1_PC4, 33 PMUX_PINGRP_SPI2_MOSI_PB4, 34 PMUX_PINGRP_SPI2_MISO_PB5, 35 PMUX_PINGRP_SPI2_SCK_PB6, 36 PMUX_PINGRP_SPI2_CS0_PB7, 37 PMUX_PINGRP_SPI2_CS1_PDD0, 38 PMUX_PINGRP_SPI4_MOSI_PC7, 39 PMUX_PINGRP_SPI4_MISO_PD0, 40 PMUX_PINGRP_SPI4_SCK_PC5, 41 PMUX_PINGRP_SPI4_CS0_PC6, 42 PMUX_PINGRP_QSPI_SCK_PEE0, 43 PMUX_PINGRP_QSPI_CS_N_PEE1, 44 PMUX_PINGRP_QSPI_IO0_PEE2, 45 PMUX_PINGRP_QSPI_IO1_PEE3, 46 PMUX_PINGRP_QSPI_IO2_PEE4, 47 PMUX_PINGRP_QSPI_IO3_PEE5, 48 PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4), 49 PMUX_PINGRP_DMIC1_DAT_PE1, 50 PMUX_PINGRP_DMIC2_CLK_PE2, 51 PMUX_PINGRP_DMIC2_DAT_PE3, 52 PMUX_PINGRP_DMIC3_CLK_PE4, 53 PMUX_PINGRP_DMIC3_DAT_PE5, 54 PMUX_PINGRP_GEN1_I2C_SCL_PJ1, 55 PMUX_PINGRP_GEN1_I2C_SDA_PJ0, 56 PMUX_PINGRP_GEN2_I2C_SCL_PJ2, 57 PMUX_PINGRP_GEN2_I2C_SDA_PJ3, 58 PMUX_PINGRP_GEN3_I2C_SCL_PF0, 59 PMUX_PINGRP_GEN3_I2C_SDA_PF1, 60 PMUX_PINGRP_CAM_I2C_SCL_PS2, 61 PMUX_PINGRP_CAM_I2C_SDA_PS3, 62 PMUX_PINGRP_PWR_I2C_SCL_PY3, 63 PMUX_PINGRP_PWR_I2C_SDA_PY4, 64 PMUX_PINGRP_UART1_TX_PU0, 65 PMUX_PINGRP_UART1_RX_PU1, 66 PMUX_PINGRP_UART1_RTS_PU2, 67 PMUX_PINGRP_UART1_CTS_PU3, 68 PMUX_PINGRP_UART2_TX_PG0, 69 PMUX_PINGRP_UART2_RX_PG1, 70 PMUX_PINGRP_UART2_RTS_PG2, 71 PMUX_PINGRP_UART2_CTS_PG3, 72 PMUX_PINGRP_UART3_TX_PD1, 73 PMUX_PINGRP_UART3_RX_PD2, 74 PMUX_PINGRP_UART3_RTS_PD3, 75 PMUX_PINGRP_UART3_CTS_PD4, 76 PMUX_PINGRP_UART4_TX_PI4, 77 PMUX_PINGRP_UART4_RX_PI5, 78 PMUX_PINGRP_UART4_RTS_PI6, 79 PMUX_PINGRP_UART4_CTS_PI7, 80 PMUX_PINGRP_DAP1_FS_PB0, 81 PMUX_PINGRP_DAP1_DIN_PB1, 82 PMUX_PINGRP_DAP1_DOUT_PB2, 83 PMUX_PINGRP_DAP1_SCLK_PB3, 84 PMUX_PINGRP_DAP2_FS_PAA0, 85 PMUX_PINGRP_DAP2_DIN_PAA2, 86 PMUX_PINGRP_DAP2_DOUT_PAA3, 87 PMUX_PINGRP_DAP2_SCLK_PAA1, 88 PMUX_PINGRP_DAP4_FS_PJ4, 89 PMUX_PINGRP_DAP4_DIN_PJ5, 90 PMUX_PINGRP_DAP4_DOUT_PJ6, 91 PMUX_PINGRP_DAP4_SCLK_PJ7, 92 PMUX_PINGRP_CAM1_MCLK_PS0, 93 PMUX_PINGRP_CAM2_MCLK_PS1, 94 PMUX_PINGRP_JTAG_RTCK, 95 PMUX_PINGRP_CLK_32K_IN, 96 PMUX_PINGRP_CLK_32K_OUT_PY5, 97 PMUX_PINGRP_BATT_BCL, 98 PMUX_PINGRP_CLK_REQ, 99 PMUX_PINGRP_CPU_PWR_REQ, 100 PMUX_PINGRP_PWR_INT_N, 101 PMUX_PINGRP_SHUTDOWN, 102 PMUX_PINGRP_CORE_PWR_REQ, 103 PMUX_PINGRP_AUD_MCLK_PBB0, 104 PMUX_PINGRP_DVFS_PWM_PBB1, 105 PMUX_PINGRP_DVFS_CLK_PBB2, 106 PMUX_PINGRP_GPIO_X1_AUD_PBB3, 107 PMUX_PINGRP_GPIO_X3_AUD_PBB4, 108 PMUX_PINGRP_PCC7, 109 PMUX_PINGRP_HDMI_CEC_PCC0, 110 PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1, 111 PMUX_PINGRP_SPDIF_OUT_PCC2, 112 PMUX_PINGRP_SPDIF_IN_PCC3, 113 PMUX_PINGRP_USB_VBUS_EN0_PCC4, 114 PMUX_PINGRP_USB_VBUS_EN1_PCC5, 115 PMUX_PINGRP_DP_HPD0_PCC6, 116 PMUX_PINGRP_WIFI_EN_PH0, 117 PMUX_PINGRP_WIFI_RST_PH1, 118 PMUX_PINGRP_WIFI_WAKE_AP_PH2, 119 PMUX_PINGRP_AP_WAKE_BT_PH3, 120 PMUX_PINGRP_BT_RST_PH4, 121 PMUX_PINGRP_BT_WAKE_AP_PH5, 122 PMUX_PINGRP_AP_WAKE_NFC_PH7, 123 PMUX_PINGRP_NFC_EN_PI0, 124 PMUX_PINGRP_NFC_INT_PI1, 125 PMUX_PINGRP_GPS_EN_PI2, 126 PMUX_PINGRP_GPS_RST_PI3, 127 PMUX_PINGRP_CAM_RST_PS4, 128 PMUX_PINGRP_CAM_AF_EN_PS5, 129 PMUX_PINGRP_CAM_FLASH_EN_PS6, 130 PMUX_PINGRP_CAM1_PWDN_PS7, 131 PMUX_PINGRP_CAM2_PWDN_PT0, 132 PMUX_PINGRP_CAM1_STROBE_PT1, 133 PMUX_PINGRP_LCD_TE_PY2, 134 PMUX_PINGRP_LCD_BL_PWM_PV0, 135 PMUX_PINGRP_LCD_BL_EN_PV1, 136 PMUX_PINGRP_LCD_RST_PV2, 137 PMUX_PINGRP_LCD_GPIO1_PV3, 138 PMUX_PINGRP_LCD_GPIO2_PV4, 139 PMUX_PINGRP_AP_READY_PV5, 140 PMUX_PINGRP_TOUCH_RST_PV6, 141 PMUX_PINGRP_TOUCH_CLK_PV7, 142 PMUX_PINGRP_MODEM_WAKE_AP_PX0, 143 PMUX_PINGRP_TOUCH_INT_PX1, 144 PMUX_PINGRP_MOTION_INT_PX2, 145 PMUX_PINGRP_ALS_PROX_INT_PX3, 146 PMUX_PINGRP_TEMP_ALERT_PX4, 147 PMUX_PINGRP_BUTTON_POWER_ON_PX5, 148 PMUX_PINGRP_BUTTON_VOL_UP_PX6, 149 PMUX_PINGRP_BUTTON_VOL_DOWN_PX7, 150 PMUX_PINGRP_BUTTON_SLIDE_SW_PY0, 151 PMUX_PINGRP_BUTTON_HOME_PY1, 152 PMUX_PINGRP_PA6, 153 PMUX_PINGRP_PE6, 154 PMUX_PINGRP_PE7, 155 PMUX_PINGRP_PH6, 156 PMUX_PINGRP_PK0, 157 PMUX_PINGRP_PK1, 158 PMUX_PINGRP_PK2, 159 PMUX_PINGRP_PK3, 160 PMUX_PINGRP_PK4, 161 PMUX_PINGRP_PK5, 162 PMUX_PINGRP_PK6, 163 PMUX_PINGRP_PK7, 164 PMUX_PINGRP_PL0, 165 PMUX_PINGRP_PL1, 166 PMUX_PINGRP_PZ0, 167 PMUX_PINGRP_PZ1, 168 PMUX_PINGRP_PZ2, 169 PMUX_PINGRP_PZ3, 170 PMUX_PINGRP_PZ4, 171 PMUX_PINGRP_PZ5, 172 PMUX_PINGRP_COUNT, 173 }; 174 175 enum pmux_drvgrp { 176 PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4), 177 PMUX_DRVGRP_AP_READY, 178 PMUX_DRVGRP_AP_WAKE_BT, 179 PMUX_DRVGRP_AP_WAKE_NFC, 180 PMUX_DRVGRP_AUD_MCLK, 181 PMUX_DRVGRP_BATT_BCL, 182 PMUX_DRVGRP_BT_RST, 183 PMUX_DRVGRP_BT_WAKE_AP, 184 PMUX_DRVGRP_BUTTON_HOME, 185 PMUX_DRVGRP_BUTTON_POWER_ON, 186 PMUX_DRVGRP_BUTTON_SLIDE_SW, 187 PMUX_DRVGRP_BUTTON_VOL_DOWN, 188 PMUX_DRVGRP_BUTTON_VOL_UP, 189 PMUX_DRVGRP_CAM1_MCLK, 190 PMUX_DRVGRP_CAM1_PWDN, 191 PMUX_DRVGRP_CAM1_STROBE, 192 PMUX_DRVGRP_CAM2_MCLK, 193 PMUX_DRVGRP_CAM2_PWDN, 194 PMUX_DRVGRP_CAM_AF_EN, 195 PMUX_DRVGRP_CAM_FLASH_EN, 196 PMUX_DRVGRP_CAM_I2C_SCL, 197 PMUX_DRVGRP_CAM_I2C_SDA, 198 PMUX_DRVGRP_CAM_RST, 199 PMUX_DRVGRP_CLK_32K_IN, 200 PMUX_DRVGRP_CLK_32K_OUT, 201 PMUX_DRVGRP_CLK_REQ, 202 PMUX_DRVGRP_CORE_PWR_REQ, 203 PMUX_DRVGRP_CPU_PWR_REQ, 204 PMUX_DRVGRP_DAP1_DIN, 205 PMUX_DRVGRP_DAP1_DOUT, 206 PMUX_DRVGRP_DAP1_FS, 207 PMUX_DRVGRP_DAP1_SCLK, 208 PMUX_DRVGRP_DAP2_DIN, 209 PMUX_DRVGRP_DAP2_DOUT, 210 PMUX_DRVGRP_DAP2_FS, 211 PMUX_DRVGRP_DAP2_SCLK, 212 PMUX_DRVGRP_DAP4_DIN, 213 PMUX_DRVGRP_DAP4_DOUT, 214 PMUX_DRVGRP_DAP4_FS, 215 PMUX_DRVGRP_DAP4_SCLK, 216 PMUX_DRVGRP_DMIC1_CLK, 217 PMUX_DRVGRP_DMIC1_DAT, 218 PMUX_DRVGRP_DMIC2_CLK, 219 PMUX_DRVGRP_DMIC2_DAT, 220 PMUX_DRVGRP_DMIC3_CLK, 221 PMUX_DRVGRP_DMIC3_DAT, 222 PMUX_DRVGRP_DP_HPD0, 223 PMUX_DRVGRP_DVFS_CLK, 224 PMUX_DRVGRP_DVFS_PWM, 225 PMUX_DRVGRP_GEN1_I2C_SCL, 226 PMUX_DRVGRP_GEN1_I2C_SDA, 227 PMUX_DRVGRP_GEN2_I2C_SCL, 228 PMUX_DRVGRP_GEN2_I2C_SDA, 229 PMUX_DRVGRP_GEN3_I2C_SCL, 230 PMUX_DRVGRP_GEN3_I2C_SDA, 231 PMUX_DRVGRP_PA6, 232 PMUX_DRVGRP_PCC7, 233 PMUX_DRVGRP_PE6, 234 PMUX_DRVGRP_PE7, 235 PMUX_DRVGRP_PH6, 236 PMUX_DRVGRP_PK0, 237 PMUX_DRVGRP_PK1, 238 PMUX_DRVGRP_PK2, 239 PMUX_DRVGRP_PK3, 240 PMUX_DRVGRP_PK4, 241 PMUX_DRVGRP_PK5, 242 PMUX_DRVGRP_PK6, 243 PMUX_DRVGRP_PK7, 244 PMUX_DRVGRP_PL0, 245 PMUX_DRVGRP_PL1, 246 PMUX_DRVGRP_PZ0, 247 PMUX_DRVGRP_PZ1, 248 PMUX_DRVGRP_PZ2, 249 PMUX_DRVGRP_PZ3, 250 PMUX_DRVGRP_PZ4, 251 PMUX_DRVGRP_PZ5, 252 PMUX_DRVGRP_GPIO_X1_AUD, 253 PMUX_DRVGRP_GPIO_X3_AUD, 254 PMUX_DRVGRP_GPS_EN, 255 PMUX_DRVGRP_GPS_RST, 256 PMUX_DRVGRP_HDMI_CEC, 257 PMUX_DRVGRP_HDMI_INT_DP_HPD, 258 PMUX_DRVGRP_JTAG_RTCK, 259 PMUX_DRVGRP_LCD_BL_EN, 260 PMUX_DRVGRP_LCD_BL_PWM, 261 PMUX_DRVGRP_LCD_GPIO1, 262 PMUX_DRVGRP_LCD_GPIO2, 263 PMUX_DRVGRP_LCD_RST, 264 PMUX_DRVGRP_LCD_TE, 265 PMUX_DRVGRP_MODEM_WAKE_AP, 266 PMUX_DRVGRP_MOTION_INT, 267 PMUX_DRVGRP_NFC_EN, 268 PMUX_DRVGRP_NFC_INT, 269 PMUX_DRVGRP_PEX_L0_CLKREQ_N, 270 PMUX_DRVGRP_PEX_L0_RST_N, 271 PMUX_DRVGRP_PEX_L1_CLKREQ_N, 272 PMUX_DRVGRP_PEX_L1_RST_N, 273 PMUX_DRVGRP_PEX_WAKE_N, 274 PMUX_DRVGRP_PWR_I2C_SCL, 275 PMUX_DRVGRP_PWR_I2C_SDA, 276 PMUX_DRVGRP_PWR_INT_N, 277 PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4), 278 PMUX_DRVGRP_SATA_LED_ACTIVE, 279 PMUX_DRVGRP_SDMMC1, 280 PMUX_DRVGRP_SDMMC2, 281 PMUX_DRVGRP_SDMMC3 = (0x1dc / 4), 282 PMUX_DRVGRP_SDMMC4, 283 PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4), 284 PMUX_DRVGRP_SPDIF_IN, 285 PMUX_DRVGRP_SPDIF_OUT, 286 PMUX_DRVGRP_SPI1_CS0, 287 PMUX_DRVGRP_SPI1_CS1, 288 PMUX_DRVGRP_SPI1_MISO, 289 PMUX_DRVGRP_SPI1_MOSI, 290 PMUX_DRVGRP_SPI1_SCK, 291 PMUX_DRVGRP_SPI2_CS0, 292 PMUX_DRVGRP_SPI2_CS1, 293 PMUX_DRVGRP_SPI2_MISO, 294 PMUX_DRVGRP_SPI2_MOSI, 295 PMUX_DRVGRP_SPI2_SCK, 296 PMUX_DRVGRP_SPI4_CS0, 297 PMUX_DRVGRP_SPI4_MISO, 298 PMUX_DRVGRP_SPI4_MOSI, 299 PMUX_DRVGRP_SPI4_SCK, 300 PMUX_DRVGRP_TEMP_ALERT, 301 PMUX_DRVGRP_TOUCH_CLK, 302 PMUX_DRVGRP_TOUCH_INT, 303 PMUX_DRVGRP_TOUCH_RST, 304 PMUX_DRVGRP_UART1_CTS, 305 PMUX_DRVGRP_UART1_RTS, 306 PMUX_DRVGRP_UART1_RX, 307 PMUX_DRVGRP_UART1_TX, 308 PMUX_DRVGRP_UART2_CTS, 309 PMUX_DRVGRP_UART2_RTS, 310 PMUX_DRVGRP_UART2_RX, 311 PMUX_DRVGRP_UART2_TX, 312 PMUX_DRVGRP_UART3_CTS, 313 PMUX_DRVGRP_UART3_RTS, 314 PMUX_DRVGRP_UART3_RX, 315 PMUX_DRVGRP_UART3_TX, 316 PMUX_DRVGRP_UART4_CTS, 317 PMUX_DRVGRP_UART4_RTS, 318 PMUX_DRVGRP_UART4_RX, 319 PMUX_DRVGRP_UART4_TX, 320 PMUX_DRVGRP_USB_VBUS_EN0, 321 PMUX_DRVGRP_USB_VBUS_EN1, 322 PMUX_DRVGRP_WIFI_EN, 323 PMUX_DRVGRP_WIFI_RST, 324 PMUX_DRVGRP_WIFI_WAKE_AP, 325 PMUX_DRVGRP_COUNT, 326 }; 327 328 enum pmux_func { 329 PMUX_FUNC_DEFAULT, 330 PMUX_FUNC_AUD, 331 PMUX_FUNC_BCL, 332 PMUX_FUNC_BLINK, 333 PMUX_FUNC_CCLA, 334 PMUX_FUNC_CEC, 335 PMUX_FUNC_CLDVFS, 336 PMUX_FUNC_CLK, 337 PMUX_FUNC_CORE, 338 PMUX_FUNC_CPU, 339 PMUX_FUNC_DISPLAYA, 340 PMUX_FUNC_DISPLAYB, 341 PMUX_FUNC_DMIC1, 342 PMUX_FUNC_DMIC2, 343 PMUX_FUNC_DMIC3, 344 PMUX_FUNC_DP, 345 PMUX_FUNC_DTV, 346 PMUX_FUNC_EXTPERIPH3, 347 PMUX_FUNC_I2C1, 348 PMUX_FUNC_I2C2, 349 PMUX_FUNC_I2C3, 350 PMUX_FUNC_I2CPMU, 351 PMUX_FUNC_I2CVI, 352 PMUX_FUNC_I2S1, 353 PMUX_FUNC_I2S2, 354 PMUX_FUNC_I2S3, 355 PMUX_FUNC_I2S4A, 356 PMUX_FUNC_I2S4B, 357 PMUX_FUNC_I2S5A, 358 PMUX_FUNC_I2S5B, 359 PMUX_FUNC_IQC0, 360 PMUX_FUNC_IQC1, 361 PMUX_FUNC_JTAG, 362 PMUX_FUNC_PE, 363 PMUX_FUNC_PE0, 364 PMUX_FUNC_PE1, 365 PMUX_FUNC_PMI, 366 PMUX_FUNC_PWM0, 367 PMUX_FUNC_PWM1, 368 PMUX_FUNC_PWM2, 369 PMUX_FUNC_PWM3, 370 PMUX_FUNC_QSPI, 371 PMUX_FUNC_SATA, 372 PMUX_FUNC_SDMMC1, 373 PMUX_FUNC_SDMMC3, 374 PMUX_FUNC_SHUTDOWN, 375 PMUX_FUNC_SOC, 376 PMUX_FUNC_SOR0, 377 PMUX_FUNC_SOR1, 378 PMUX_FUNC_SPDIF, 379 PMUX_FUNC_SPI1, 380 PMUX_FUNC_SPI2, 381 PMUX_FUNC_SPI3, 382 PMUX_FUNC_SPI4, 383 PMUX_FUNC_SYS, 384 PMUX_FUNC_TOUCH, 385 PMUX_FUNC_UART, 386 PMUX_FUNC_UARTA, 387 PMUX_FUNC_UARTB, 388 PMUX_FUNC_UARTC, 389 PMUX_FUNC_UARTD, 390 PMUX_FUNC_USB, 391 PMUX_FUNC_VGP1, 392 PMUX_FUNC_VGP2, 393 PMUX_FUNC_VGP3, 394 PMUX_FUNC_VGP4, 395 PMUX_FUNC_VGP5, 396 PMUX_FUNC_VGP6, 397 PMUX_FUNC_VIMCLK, 398 PMUX_FUNC_VIMCLK2, 399 PMUX_FUNC_RSVD0, 400 PMUX_FUNC_RSVD1, 401 PMUX_FUNC_RSVD2, 402 PMUX_FUNC_RSVD3, 403 PMUX_FUNC_COUNT, 404 }; 405 406 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 407 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING 408 #define TEGRA_PMX_SOC_HAS_DRVGRPS 409 #define TEGRA_PMX_PINS_HAVE_E_INPUT 410 #define TEGRA_PMX_PINS_HAVE_LOCK 411 #define TEGRA_PMX_PINS_HAVE_OD 412 #define TEGRA_PMX_PINS_HAVE_E_IO_HV 413 #include <asm/arch-tegra/pinmux.h> 414 415 #endif /* _TEGRA210_PINMUX_H_ */ 416
