1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Vipin Kumar, ST Micoelectronics, vipin.kumar (at) st.com. 5 */ 6 7 #ifndef ST_SMI_H 8 #define ST_SMI_H 9 10 /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ 11 /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ 12 13 #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE 14 #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE 15 16 #define SMIBANK0_BASE (FLASH_START_ADDRESS) 17 #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) 18 #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) 19 #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) 20 21 #define BANK0 0 22 #define BANK1 1 23 #define BANK2 2 24 #define BANK3 3 25 26 struct smi_regs { 27 u32 smi_cr1; 28 u32 smi_cr2; 29 u32 smi_sr; 30 u32 smi_tr; 31 u32 smi_rr; 32 }; 33 34 /* CONTROL REG 1 */ 35 #define BANK_EN 0x0000000F /* enables all banks */ 36 #define DSEL_TIME 0x00000060 /* Deselect time */ 37 #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ 38 #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ 39 #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ 40 #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ 41 #define SW_MODE 0x10000000 /* enables SW Mode */ 42 #define WB_MODE 0x20000000 /* Write Burst Mode */ 43 #define FAST_MODE 0x00008000 /* Fast Mode */ 44 #define HOLD1 0x00010000 45 46 /* CONTROL REG 2 */ 47 #define RD_STATUS_REG 0x00000400 /* reads status reg */ 48 #define WE 0x00000800 /* Write Enable */ 49 #define BANK0_SEL 0x00000000 /* Select Banck0 */ 50 #define BANK1_SEL 0x00001000 /* Select Banck1 */ 51 #define BANK2_SEL 0x00002000 /* Select Banck2 */ 52 #define BANK3_SEL 0x00003000 /* Select Banck3 */ 53 #define BANKSEL_SHIFT 12 54 #define SEND 0x00000080 /* Send data */ 55 #define TX_LEN_1 0x00000001 /* data length = 1 byte */ 56 #define TX_LEN_2 0x00000002 /* data length = 2 byte */ 57 #define TX_LEN_3 0x00000003 /* data length = 3 byte */ 58 #define TX_LEN_4 0x00000004 /* data length = 4 byte */ 59 #define RX_LEN_1 0x00000010 /* data length = 1 byte */ 60 #define RX_LEN_2 0x00000020 /* data length = 2 byte */ 61 #define RX_LEN_3 0x00000030 /* data length = 3 byte */ 62 #define RX_LEN_4 0x00000040 /* data length = 4 byte */ 63 #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ 64 #define WCIE 0x00000200 /* WCF Interrupt Enable */ 65 66 /* STATUS_REG */ 67 #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ 68 #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ 69 #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ 70 #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ 71 #define RSR 0x00000005 /* Read Status regiser */ 72 #define TFF 0x00000100 /* Transfer Finished FLag */ 73 #define WCF 0x00000200 /* Transfer Finished FLag */ 74 #define ERF1 0x00000400 /* Error Flag 1 */ 75 #define ERF2 0x00000800 /* Error Flag 2 */ 76 #define WM0 0x00001000 /* WM Bank 0 */ 77 #define WM1 0x00002000 /* WM Bank 1 */ 78 #define WM2 0x00004000 /* WM Bank 2 */ 79 #define WM3 0x00008000 /* WM Bank 3 */ 80 #define WM_SHIFT 12 81 82 /* TR REG */ 83 #define READ_ID 0x0000009F /* Read Identification */ 84 #define BULK_ERASE 0x000000C7 /* BULK erase */ 85 #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ 86 #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ 87 88 struct flash_dev { 89 u32 density; 90 ulong size; 91 ushort sector_count; 92 }; 93 94 #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ 95 #define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ 96 #define WMODE_TOUT 15 /* write enable timeout(in ms) */ 97 98 extern void smi_init(void); 99 100 #endif 101
