| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 144 unsigned UseIdx = 0;
148 ++UseIdx;
150 return UseIdx;
202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
|
| LiveRangeCalc.cpp | 186 SlotIndex UseIdx;
191 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
203 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
208 extend(LR, UseIdx, Reg);
|
| TwoAddressInstructionPass.cpp | 416 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
417 LiveInterval::const_iterator I = LI.find(useIdx);
419 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
[all...] |
| MachineVerifier.cpp | 230 SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
[all...] |
| RegisterCoalescer.cpp | 213 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
705 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
706 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
759 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
760 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
780 SlotIndex DefIdx = UseIdx.getRegSlot();
[all...] |
| MachinePipeliner.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| MachineCombiner.cpp | 188 int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
190 InstrPtr, UseIdx);
|
| TargetSchedule.cpp | 175 unsigned UseIdx = 0;
179 ++UseIdx;
181 return UseIdx;
233 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
234 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
|
| LiveRangeCalc.cpp | 190 SlotIndex UseIdx;
195 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
207 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
212 extend(LR, UseIdx, Reg, Undefs);
|
| TwoAddressInstructionPass.cpp | 445 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
446 LiveInterval::const_iterator I = LI.find(useIdx);
448 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
[all...] |
| MachineVerifier.cpp | 260 SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
[all...] |
| RegisterCoalescer.cpp | 233 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
755 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
756 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
809 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
810 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
830 SlotIndex DefIdx = UseIdx.getRegSlot();
[all...] |
| MachinePipeliner.cpp | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCSchedule.h | 84 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
87 unsigned UseIdx;
92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 672 int UseIdx = SwapMap[&UseMI];
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
675 SwapVector[UseIdx].IsStore) {
683 DEBUG(dbgs() << " use " << UseIdx << ": ");
715 int UseIdx = SwapMap[&UseMI];
717 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) {
725 DEBUG(dbgs() << " use " << UseIdx << ": ");
726 DEBUG(SwapVector[UseIdx].VSEMI->dump());
756 int UseIdx = SwapMap[&UseMI]
[all...] |
| PPCInstrInfo.cpp | 144 unsigned UseIdx) const {
146 UseMI, UseIdx);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| MCSchedule.h | 93 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
96 unsigned UseIdx;
101 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 350 unsigned UseIdx = -1;
354 UseIdx = OpNum;
359 0, *DDst, UseIdx));
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 681 int UseIdx = SwapMap[&UseMI];
683 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
684 SwapVector[UseIdx].IsStore) {
692 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": ");
724 int UseIdx = SwapMap[&UseMI];
726 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) {
735 LLVM_DEBUG(dbgs() << " use " << UseIdx << ": ");
736 LLVM_DEBUG(SwapVector[UseIdx].VSEMI->dump());
766 int UseIdx = SwapMap[&UseMI]
[all...] |
| PPCInstrInfo.cpp | 180 unsigned UseIdx) const {
182 UseMI, UseIdx);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| MachineVerifier.cpp | 662 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
665 if (!LI.liveAt(UseIdx)) {
667 *OS << UseIdx << " is not live in " << LI << '\n';
671 if (MO->isKill() && !LI.killedAt(UseIdx.getDefIndex())) {
[all...] |
| InlineSpiller.cpp | 836 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex();
837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
846 DEBUG(dbgs() << UseIdx << '\t' << *MI);
858 if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) {
860 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
874 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
[all...] |
| LiveIntervalAnalysis.cpp | [all...] |
| RegisterCoalescer.cpp | 698 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
699 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
750 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getUseIndex();
751 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
768 SlotIndex DefIdx = UseIdx.getDefIndex();
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 717 unsigned UseIdx;
725 UseIdx = 2;
727 UseIdx = 2, CommuteIdx = 1;
736 UseIdx = 2;
738 UseIdx = 2, CommuteIdx = 1;
747 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
752 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
[all...] |
