1 /* SPDX-License-Identifier: Intel */ 2 /* 3 * Copyright (C) 2013, Intel Corporation 4 * Copyright (C) 2015, Bin Meng <bmeng.cn (at) gmail.com> 5 * 6 * Ported from Intel released Quark UEFI BIOS 7 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei 8 */ 9 10 #ifndef _MRC_UTIL_H_ 11 #define _MRC_UTIL_H_ 12 13 /* Turn on this macro to enable MRC debugging output */ 14 #undef MRC_DEBUG 15 16 /* MRC Debug Support */ 17 #define DPF debug_cond 18 19 /* debug print type */ 20 21 #ifdef MRC_DEBUG 22 #define D_ERROR 0x0001 23 #define D_INFO 0x0002 24 #define D_REGRD 0x0004 25 #define D_REGWR 0x0008 26 #define D_FCALL 0x0010 27 #define D_TRN 0x0020 28 #define D_TIME 0x0040 29 #else 30 #define D_ERROR 0 31 #define D_INFO 0 32 #define D_REGRD 0 33 #define D_REGWR 0 34 #define D_FCALL 0 35 #define D_TRN 0 36 #define D_TIME 0 37 #endif 38 39 #define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__) 40 #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__) 41 #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) 42 43 /* Message Bus Port */ 44 #define MEM_CTLR 0x01 45 #define HOST_BRIDGE 0x03 46 #define MEM_MGR 0x05 47 #define HTE 0x11 48 #define DDRPHY 0x12 49 50 /* number of sample points */ 51 #define SAMPLE_CNT 3 52 /* number of PIs to increment per sample */ 53 #define SAMPLE_DLY 26 54 55 enum { 56 /* indicates to decrease delays when looking for edge */ 57 BACKWARD, 58 /* indicates to increase delays when looking for edge */ 59 FORWARD 60 }; 61 62 enum { 63 RCVN, 64 WDQS, 65 WDQX, 66 RDQS, 67 VREF, 68 WCMD, 69 WCTL, 70 WCLK, 71 MAX_ALGOS, 72 }; 73 74 void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask); 75 void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask); 76 void mrc_post_code(uint8_t major, uint8_t minor); 77 void delay_n(uint32_t ns); 78 void delay_u(uint32_t ms); 79 void select_mem_mgr(void); 80 void select_hte(void); 81 void dram_init_command(uint32_t data); 82 void dram_wake_command(void); 83 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane); 84 85 void set_rcvn(uint8_t channel, uint8_t rank, 86 uint8_t byte_lane, uint32_t pi_count); 87 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane); 88 void set_rdqs(uint8_t channel, uint8_t rank, 89 uint8_t byte_lane, uint32_t pi_count); 90 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); 91 void set_wdqs(uint8_t channel, uint8_t rank, 92 uint8_t byte_lane, uint32_t pi_count); 93 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); 94 void set_wdq(uint8_t channel, uint8_t rank, 95 uint8_t byte_lane, uint32_t pi_count); 96 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane); 97 void set_wcmd(uint8_t channel, uint32_t pi_count); 98 uint32_t get_wcmd(uint8_t channel); 99 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count); 100 uint32_t get_wclk(uint8_t channel, uint8_t rank); 101 void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count); 102 uint32_t get_wctl(uint8_t channel, uint8_t rank); 103 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting); 104 uint32_t get_vref(uint8_t channel, uint8_t byte_lane); 105 106 uint32_t get_addr(uint8_t channel, uint8_t rank); 107 uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, 108 uint8_t rank, bool rcvn); 109 void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], 110 uint8_t channel, uint8_t rank, bool rcvn); 111 uint32_t byte_lane_mask(struct mrc_params *mrc_params); 112 uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address); 113 uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address); 114 void lfsr32(uint32_t *lfsr_ptr); 115 void clear_pointers(void); 116 void print_timings(struct mrc_params *mrc_params); 117 118 #endif /* _MRC_UTIL_H_ */ 119
