1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-12-19 18:19:46) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2018-01-03 15:58:51) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-12-19 18:19:46) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 146261 bytes, from 2018-01-03 15:58:51) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27) 20 21 Copyright (C) 2013-2017 by the following authors: 22 - Rob Clark <robdclark (at) gmail.com> (robclark) 23 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum chip { 48 A2XX = 0, 49 A3XX = 0, 50 A4XX = 0, 51 A5XX = 0, 52 }; 53 54 enum adreno_pa_su_sc_draw { 55 PC_DRAW_POINTS = 0, 56 PC_DRAW_LINES = 1, 57 PC_DRAW_TRIANGLES = 2, 58 }; 59 60 enum adreno_compare_func { 61 FUNC_NEVER = 0, 62 FUNC_LESS = 1, 63 FUNC_EQUAL = 2, 64 FUNC_LEQUAL = 3, 65 FUNC_GREATER = 4, 66 FUNC_NOTEQUAL = 5, 67 FUNC_GEQUAL = 6, 68 FUNC_ALWAYS = 7, 69 }; 70 71 enum adreno_stencil_op { 72 STENCIL_KEEP = 0, 73 STENCIL_ZERO = 1, 74 STENCIL_REPLACE = 2, 75 STENCIL_INCR_CLAMP = 3, 76 STENCIL_DECR_CLAMP = 4, 77 STENCIL_INVERT = 5, 78 STENCIL_INCR_WRAP = 6, 79 STENCIL_DECR_WRAP = 7, 80 }; 81 82 enum adreno_rb_blend_factor { 83 FACTOR_ZERO = 0, 84 FACTOR_ONE = 1, 85 FACTOR_SRC_COLOR = 4, 86 FACTOR_ONE_MINUS_SRC_COLOR = 5, 87 FACTOR_SRC_ALPHA = 6, 88 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 89 FACTOR_DST_COLOR = 8, 90 FACTOR_ONE_MINUS_DST_COLOR = 9, 91 FACTOR_DST_ALPHA = 10, 92 FACTOR_ONE_MINUS_DST_ALPHA = 11, 93 FACTOR_CONSTANT_COLOR = 12, 94 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 95 FACTOR_CONSTANT_ALPHA = 14, 96 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 97 FACTOR_SRC_ALPHA_SATURATE = 16, 98 FACTOR_SRC1_COLOR = 20, 99 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 100 FACTOR_SRC1_ALPHA = 22, 101 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 102 }; 103 104 enum adreno_rb_surface_endian { 105 ENDIAN_NONE = 0, 106 ENDIAN_8IN16 = 1, 107 ENDIAN_8IN32 = 2, 108 ENDIAN_16IN32 = 3, 109 ENDIAN_8IN64 = 4, 110 ENDIAN_8IN128 = 5, 111 }; 112 113 enum adreno_rb_dither_mode { 114 DITHER_DISABLE = 0, 115 DITHER_ALWAYS = 1, 116 DITHER_IF_ALPHA_OFF = 2, 117 }; 118 119 enum adreno_rb_depth_format { 120 DEPTHX_16 = 0, 121 DEPTHX_24_8 = 1, 122 DEPTHX_32 = 2, 123 }; 124 125 enum adreno_rb_copy_control_mode { 126 RB_COPY_RESOLVE = 1, 127 RB_COPY_CLEAR = 2, 128 RB_COPY_DEPTH_STENCIL = 5, 129 }; 130 131 enum a3xx_rop_code { 132 ROP_CLEAR = 0, 133 ROP_NOR = 1, 134 ROP_AND_INVERTED = 2, 135 ROP_COPY_INVERTED = 3, 136 ROP_AND_REVERSE = 4, 137 ROP_INVERT = 5, 138 ROP_XOR = 6, 139 ROP_NAND = 7, 140 ROP_AND = 8, 141 ROP_EQUIV = 9, 142 ROP_NOOP = 10, 143 ROP_OR_INVERTED = 11, 144 ROP_COPY = 12, 145 ROP_OR_REVERSE = 13, 146 ROP_OR = 14, 147 ROP_SET = 15, 148 }; 149 150 enum a3xx_render_mode { 151 RB_RENDERING_PASS = 0, 152 RB_TILING_PASS = 1, 153 RB_RESOLVE_PASS = 2, 154 RB_COMPUTE_PASS = 3, 155 }; 156 157 enum a3xx_msaa_samples { 158 MSAA_ONE = 0, 159 MSAA_TWO = 1, 160 MSAA_FOUR = 2, 161 }; 162 163 enum a3xx_threadmode { 164 MULTI = 0, 165 SINGLE = 1, 166 }; 167 168 enum a3xx_instrbuffermode { 169 CACHE = 0, 170 BUFFER = 1, 171 }; 172 173 enum a3xx_threadsize { 174 TWO_QUADS = 0, 175 FOUR_QUADS = 1, 176 }; 177 178 enum a3xx_color_swap { 179 WZYX = 0, 180 WXYZ = 1, 181 ZYXW = 2, 182 XYZW = 3, 183 }; 184 185 enum a3xx_rb_blend_opcode { 186 BLEND_DST_PLUS_SRC = 0, 187 BLEND_SRC_MINUS_DST = 1, 188 BLEND_DST_MINUS_SRC = 2, 189 BLEND_MIN_DST_SRC = 3, 190 BLEND_MAX_DST_SRC = 4, 191 }; 192 193 enum a4xx_tess_spacing { 194 EQUAL_SPACING = 0, 195 ODD_SPACING = 2, 196 EVEN_SPACING = 3, 197 }; 198 199 #define REG_AXXX_CP_RB_BASE 0x000001c0 200 201 #define REG_AXXX_CP_RB_CNTL 0x000001c1 202 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 203 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 204 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 205 { 206 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 207 } 208 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 209 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 210 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 211 { 212 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 213 } 214 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 215 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 216 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 217 { 218 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 219 } 220 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 221 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 222 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 223 224 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 225 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 226 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 227 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 228 { 229 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 230 } 231 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 232 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 233 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 234 { 235 assert(!(val & 0x3)); 236 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 237 } 238 239 #define REG_AXXX_CP_RB_RPTR 0x000001c4 240 241 #define REG_AXXX_CP_RB_WPTR 0x000001c5 242 243 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 244 245 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 246 247 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 248 249 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 250 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 251 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 252 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 253 { 254 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 255 } 256 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 257 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 258 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 259 { 260 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 261 } 262 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 263 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 264 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 265 { 266 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 267 } 268 269 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 270 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 271 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 272 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 273 { 274 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 275 } 276 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 277 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 278 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 279 { 280 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 281 } 282 283 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 284 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 285 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 286 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 287 { 288 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 289 } 290 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 291 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 292 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 293 { 294 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 295 } 296 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 297 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 298 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 299 { 300 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 301 } 302 303 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 304 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 305 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 306 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 307 { 308 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 309 } 310 311 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 312 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 313 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 314 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 315 { 316 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 317 } 318 319 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 320 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 321 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 322 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 323 { 324 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 325 } 326 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 327 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 328 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 329 { 330 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 331 } 332 333 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 334 335 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 336 337 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 338 339 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 340 341 #define REG_AXXX_CP_INT_CNTL 0x000001f2 342 343 #define REG_AXXX_CP_INT_STATUS 0x000001f3 344 345 #define REG_AXXX_CP_INT_ACK 0x000001f4 346 347 #define REG_AXXX_CP_ME_CNTL 0x000001f6 348 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 349 #define AXXX_CP_ME_CNTL_HALT 0x10000000 350 351 #define REG_AXXX_CP_ME_STATUS 0x000001f7 352 353 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 354 355 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 356 357 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 358 359 #define REG_AXXX_CP_DEBUG 0x000001fc 360 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 361 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 362 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 363 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 364 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 365 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 366 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 367 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 368 369 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 370 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 371 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 372 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 373 { 374 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 375 } 376 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 377 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 378 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 379 { 380 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 381 } 382 383 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 384 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 385 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 386 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 387 { 388 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 389 } 390 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 391 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 392 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 393 { 394 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 395 } 396 397 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 398 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 399 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 400 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 401 { 402 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 403 } 404 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 405 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 406 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 407 { 408 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 409 } 410 411 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 412 413 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 414 415 #define REG_AXXX_CP_ST_BASE 0x0000044d 416 417 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 418 419 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 420 421 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 422 423 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 424 425 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 426 427 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 428 429 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 430 431 #define REG_AXXX_CP_IB1_BASE 0x00000458 432 433 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 434 435 #define REG_AXXX_CP_IB2_BASE 0x0000045a 436 437 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 438 439 #define REG_AXXX_CP_STAT 0x0000047f 440 #define AXXX_CP_STAT_CP_BUSY 0x80000000 441 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 442 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 443 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 444 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 445 #define AXXX_CP_STAT_ME_BUSY 0x04000000 446 #define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 447 #define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 448 #define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 449 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 450 #define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 451 #define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 452 #define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 453 #define AXXX_CP_STAT_PFP_BUSY 0x00020000 454 #define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 455 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 456 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 457 #define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 458 #define AXXX_CP_STAT_CSF_BUSY 0x00000400 459 #define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 460 #define AXXX_CP_STAT_EVENT_BUSY 0x00000100 461 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 462 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 463 #define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 464 #define AXXX_CP_STAT_RCIU_BUSY 0x00000010 465 #define AXXX_CP_STAT_RBIU_BUSY 0x00000008 466 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 467 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 468 #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 469 470 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 471 472 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 473 474 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 475 476 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 477 478 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 479 480 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 481 482 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 483 484 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 485 486 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 487 488 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 489 490 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 491 492 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 493 494 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 495 496 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 497 498 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 499 500 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 501 502 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 503 504 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 505 506 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 507 508 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 509 510 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 511 512 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 513 514 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 515 516 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 517 518 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 519 520 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 521 522 523 #endif /* ADRENO_COMMON_XML */ 524
