1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] 4 * 5 * Copyright (C) 2005 Ivan Kokshaysky 6 * Copyright (C) SAN People 7 * Copyright (C) 2009 Jens Scharsig (js_at_ng (at) scharsoft.de) 8 * 9 * Parallel I/O Controller (PIO) - System peripherals registers. 10 * Based on AT91RM9200 datasheet revision E. 11 */ 12 13 #ifndef AT91_PIO_H 14 #define AT91_PIO_H 15 16 17 #define AT91_ASM_PIO_RANGE 0x200 18 #define AT91_ASM_PIOC_ASR \ 19 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) 20 #define AT91_ASM_PIOC_BSR \ 21 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) 22 #define AT91_ASM_PIOC_PDR \ 23 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) 24 #define AT91_ASM_PIOC_PUDR \ 25 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) 26 27 #define AT91_ASM_PIOD_PDR \ 28 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) 29 #define AT91_ASM_PIOD_PUDR \ 30 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) 31 #define AT91_ASM_PIOD_ASR \ 32 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) 33 34 #define PIO_SCDR_DIV 0x3fff /* Slow Clock Divider Selection for Debouncing Mask */ 35 36 #ifndef __ASSEMBLY__ 37 38 typedef struct at91_port { 39 u32 per; /* 0x00 PIO Enable Register */ 40 u32 pdr; /* 0x04 PIO Disable Register */ 41 u32 psr; /* 0x08 PIO Status Register */ 42 u32 reserved0; 43 u32 oer; /* 0x10 Output Enable Register */ 44 u32 odr; /* 0x14 Output Disable Registerr */ 45 u32 osr; /* 0x18 Output Status Register */ 46 u32 reserved1; 47 u32 ifer; /* 0x20 Input Filter Enable Register */ 48 u32 ifdr; /* 0x24 Input Filter Disable Register */ 49 u32 ifsr; /* 0x28 Input Filter Status Register */ 50 u32 reserved2; 51 u32 sodr; /* 0x30 Set Output Data Register */ 52 u32 codr; /* 0x34 Clear Output Data Register */ 53 u32 odsr; /* 0x38 Output Data Status Register */ 54 u32 pdsr; /* 0x3C Pin Data Status Register */ 55 u32 ier; /* 0x40 Interrupt Enable Register */ 56 u32 idr; /* 0x44 Interrupt Disable Register */ 57 u32 imr; /* 0x48 Interrupt Mask Register */ 58 u32 isr; /* 0x4C Interrupt Status Register */ 59 u32 mder; /* 0x50 Multi-driver Enable Register */ 60 u32 mddr; /* 0x54 Multi-driver Disable Register */ 61 u32 mdsr; /* 0x58 Multi-driver Status Register */ 62 u32 reserved3; 63 u32 pudr; /* 0x60 Pull-up Disable Register */ 64 u32 puer; /* 0x64 Pull-up Enable Register */ 65 u32 pusr; /* 0x68 Pad Pull-up Status Register */ 66 u32 reserved4; 67 union { 68 struct { 69 u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ 70 u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ 71 u32 reserved5[2]; 72 u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ 73 u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ 74 u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ 75 u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ 76 u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ 77 u32 ppder; /* 0x94 Pad Pull-down Enable Register */ 78 u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ 79 u32 reserved6; /* */ 80 } pio3; 81 82 struct { 83 u32 asr; /* 0x70 Select A Register */ 84 u32 bsr; /* 0x74 Select B Register */ 85 u32 absr; /* 0x78 AB Select Status Register */ 86 u32 reserved5[9]; /* */ 87 } pio2; 88 } mux; 89 90 u32 ower; /* 0xA0 Output Write Enable Register */ 91 u32 owdr; /* 0xA4 Output Write Disable Register */ 92 u32 owsr; /* OxA8 Output Write Status Register */ 93 u32 reserved7; /* */ 94 u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ 95 u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ 96 u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ 97 u32 reserved8; /* */ 98 u32 esr; /* 0xC0 Edge Select Register */ 99 u32 lsr; /* 0xC4 Level Select Register */ 100 u32 elsr; /* 0xC8 Edge/Level Status Register */ 101 u32 reserved9; /* 0xCC */ 102 u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ 103 u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ 104 u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ 105 u32 reserved10; /* */ 106 u32 locksr; /* 0xE0 Lock Status */ 107 u32 wpmr; /* 0xE4 Write Protect Mode Register */ 108 u32 wpsr; /* 0xE8 Write Protect Status Register */ 109 u32 reserved11[5]; /* */ 110 u32 schmitt; /* 0x100 Schmitt Trigger Register */ 111 u32 reserved12[4]; /* 0x104 ~ 0x110 */ 112 u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */ 113 u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */ 114 u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */ 115 u32 reserved13[12]; /* 0x120 ~ 0x14C */ 116 } at91_port_t; 117 118 typedef union at91_pio { 119 struct { 120 at91_port_t pioa; 121 at91_port_t piob; 122 at91_port_t pioc; 123 at91_port_t piod; /* not present in all hardware */ 124 at91_port_t pioe;/* not present in all hardware */ 125 }; 126 at91_port_t port[5]; 127 } at91_pio_t; 128 129 #ifdef CONFIG_AT91_GPIO 130 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); 131 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); 132 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); 133 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); 134 int at91_set_pio_output(unsigned port, unsigned pin, int value); 135 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); 136 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); 137 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); 138 int at91_set_pio_value(unsigned port, unsigned pin, int value); 139 int at91_get_pio_value(unsigned port, unsigned pin); 140 141 int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup); 142 int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup); 143 int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup); 144 int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup); 145 int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); 146 int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); 147 int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on); 148 int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); 149 #endif 150 #endif 151 152 #define AT91_PIO_PORTA 0x0 153 #define AT91_PIO_PORTB 0x1 154 #define AT91_PIO_PORTC 0x2 155 #define AT91_PIO_PORTD 0x3 156 #define AT91_PIO_PORTE 0x4 157 158 #endif 159
