1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <console.h> 9 #include <debug.h> 10 #include <mmio.h> 11 #include <plat_arm.h> 12 #include <platform.h> 13 #include <platform_def.h> 14 #include <platform_sp_min.h> 15 16 #define BL32_END (uintptr_t)(&__BL32_END__) 17 18 static entry_point_info_t bl33_image_ep_info; 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak sp_min_early_platform_setup 22 #pragma weak sp_min_platform_setup 23 #pragma weak sp_min_plat_arch_setup 24 25 26 /******************************************************************************* 27 * Return a pointer to the 'entry_point_info' structure of the next image for the 28 * security state specified. BL33 corresponds to the non-secure image type 29 * while BL32 corresponds to the secure image type. A NULL pointer is returned 30 * if the image does not exist. 31 ******************************************************************************/ 32 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 33 { 34 entry_point_info_t *next_image_info; 35 36 next_image_info = &bl33_image_ep_info; 37 38 /* 39 * None of the images on the ARM development platforms can have 0x0 40 * as the entrypoint 41 */ 42 if (next_image_info->pc) 43 return next_image_info; 44 else 45 return NULL; 46 } 47 48 /******************************************************************************* 49 * Perform early platform setup. 50 ******************************************************************************/ 51 void arm_sp_min_early_platform_setup(void *from_bl2, 52 void *plat_params_from_bl2) 53 { 54 /* Initialize the console to provide early debug support */ 55 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 56 ARM_CONSOLE_BAUDRATE); 57 58 #if RESET_TO_SP_MIN 59 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 60 assert(from_bl2 == NULL); 61 assert(plat_params_from_bl2 == NULL); 62 63 /* Populate entry point information for BL33 */ 64 SET_PARAM_HEAD(&bl33_image_ep_info, 65 PARAM_EP, 66 VERSION_1, 67 0); 68 /* 69 * Tell SP_MIN where the non-trusted software image 70 * is located and the entry state information 71 */ 72 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 73 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 74 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 75 76 #else /* RESET_TO_SP_MIN */ 77 78 /* 79 * Check params passed from BL2 should not be NULL, 80 */ 81 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 82 assert(params_from_bl2 != NULL); 83 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 84 assert(params_from_bl2->h.version >= VERSION_2); 85 86 bl_params_node_t *bl_params = params_from_bl2->head; 87 88 /* 89 * Copy BL33 entry point information. 90 * They are stored in Secure RAM, in BL2's address space. 91 */ 92 while (bl_params) { 93 if (bl_params->image_id == BL33_IMAGE_ID) { 94 bl33_image_ep_info = *bl_params->ep_info; 95 break; 96 } 97 98 bl_params = bl_params->next_params_info; 99 } 100 101 if (bl33_image_ep_info.pc == 0) 102 panic(); 103 104 #endif /* RESET_TO_SP_MIN */ 105 106 } 107 108 void sp_min_early_platform_setup(void *from_bl2, 109 void *plat_params_from_bl2) 110 { 111 arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); 112 113 /* 114 * Initialize Interconnect for this cluster during cold boot. 115 * No need for locks as no other CPU is active. 116 */ 117 plat_arm_interconnect_init(); 118 119 /* 120 * Enable Interconnect coherency for the primary CPU's cluster. 121 * Earlier bootloader stages might already do this (e.g. Trusted 122 * Firmware's BL1 does it) but we can't assume so. There is no harm in 123 * executing this code twice anyway. 124 * Platform specific PSCI code will enable coherency for other 125 * clusters. 126 */ 127 plat_arm_interconnect_enter_coherency(); 128 } 129 130 /******************************************************************************* 131 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 132 * Common to ARM standard platforms. 133 ******************************************************************************/ 134 void arm_sp_min_plat_runtime_setup(void) 135 { 136 /* Initialize the runtime console */ 137 console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE, 138 PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); 139 } 140 141 /******************************************************************************* 142 * Perform platform specific setup for SP_MIN 143 ******************************************************************************/ 144 void sp_min_platform_setup(void) 145 { 146 /* Initialize the GIC driver, cpu and distributor interfaces */ 147 plat_arm_gic_driver_init(); 148 plat_arm_gic_init(); 149 150 /* 151 * Do initial security configuration to allow DRAM/device access 152 * (if earlier BL has not already done so). 153 */ 154 #if RESET_TO_SP_MIN 155 plat_arm_security_setup(); 156 #endif 157 158 /* Enable and initialize the System level generic timer */ 159 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 160 CNTCR_FCREQ(0) | CNTCR_EN); 161 162 /* Allow access to the System counter timer module */ 163 arm_configure_sys_timer(); 164 165 /* Initialize power controller before setting up topology */ 166 plat_arm_pwrc_setup(); 167 } 168 169 void sp_min_plat_runtime_setup(void) 170 { 171 arm_sp_min_plat_runtime_setup(); 172 } 173 174 /******************************************************************************* 175 * Perform the very early platform specific architectural setup here. At the 176 * moment this only initializes the MMU 177 ******************************************************************************/ 178 void sp_min_plat_arch_setup(void) 179 { 180 181 arm_setup_page_tables(BL32_BASE, 182 (BL32_END - BL32_BASE), 183 BL_CODE_BASE, 184 BL_CODE_END, 185 BL_RO_DATA_BASE, 186 BL_RO_DATA_END 187 #if USE_COHERENT_MEM 188 , BL_COHERENT_RAM_BASE, 189 BL_COHERENT_RAM_END 190 #endif 191 ); 192 193 enable_mmu_secure(0); 194 } 195
