1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Samsung Electronics 4 * R. Chandrasekar <rcsekar (at) samsung.com> 5 */ 6 7 #ifndef __I2S_H__ 8 #define __I2S_H__ 9 10 /* 11 * DAI hardware audio formats. 12 * 13 * Describes the physical PCM data formating and clocking. Add new formats 14 * to the end. 15 */ 16 #define SND_SOC_DAIFMT_I2S 1 /* I2S mode */ 17 #define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */ 18 #define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */ 19 #define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */ 20 #define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */ 21 #define SND_SOC_DAIFMT_AC97 6 /* AC97 */ 22 #define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */ 23 24 /* left and right justified also known as MSB and LSB respectively */ 25 #define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J 26 #define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J 27 28 /* 29 * DAI hardware signal inversions. 30 * 31 * Specifies whether the DAI can also support inverted clocks for the specified 32 * format. 33 */ 34 #define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */ 35 #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ 36 #define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ 37 #define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ 38 39 /* 40 * DAI hardware clock masters. 41 * 42 * This is wrt the codec, the inverse is true for the interface 43 * i.e. if the codec is clk and FRM master then the interface is 44 * clk and frame slave. 45 */ 46 #define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */ 47 #define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */ 48 #define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */ 49 #define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */ 50 51 #define SND_SOC_DAIFMT_FORMAT_MASK 0x000f 52 #define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 53 #define SND_SOC_DAIFMT_INV_MASK 0x0f00 54 #define SND_SOC_DAIFMT_MASTER_MASK 0xf000 55 56 /* 57 * Master Clock Directions 58 */ 59 #define SND_SOC_CLOCK_IN 0 60 #define SND_SOC_CLOCK_OUT 1 61 62 /* I2S Tx Control */ 63 #define I2S_TX_ON 1 64 #define I2S_TX_OFF 0 65 66 #define FIFO_LENGTH 64 67 68 /* I2s Registers */ 69 struct i2s_reg { 70 unsigned int con; /* base + 0 , Control register */ 71 unsigned int mod; /* Mode register */ 72 unsigned int fic; /* FIFO control register */ 73 unsigned int psr; /* Reserved */ 74 unsigned int txd; /* Transmit data register */ 75 unsigned int rxd; /* Receive Data Register */ 76 }; 77 78 /* This structure stores the i2s related information */ 79 struct i2stx_info { 80 unsigned int rfs; /* LR clock frame size */ 81 unsigned int bfs; /* Bit slock frame size */ 82 unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ 83 unsigned int samplingrate; /* sampling rate */ 84 unsigned int bitspersample; /* bits per sample */ 85 unsigned int channels; /* audio channels */ 86 unsigned int base_address; /* I2S Register Base */ 87 unsigned int id; /* I2S controller id */ 88 }; 89 90 /* 91 * Sends the given data through i2s tx 92 * 93 * @param pi2s_tx pointer of i2s transmitter parameter structure. 94 * @param data address of the data buffer 95 * @param data_size array size of the int buffer (total size / size of int) 96 * 97 * @return int value 0 for success, -1 in case of error 98 */ 99 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data, 100 unsigned long data_size); 101 102 /* 103 * Initialise i2s transmiter 104 * 105 * @param pi2s_tx pointer of i2s transmitter parameter structure. 106 * 107 * @return int value 0 for success, -1 in case of error 108 */ 109 int i2s_tx_init(struct i2stx_info *pi2s_tx); 110 111 #endif /* __I2S_H__ */ 112
