1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <interrupt_mgmt.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <pubsub_events.h> 17 #include <smcc_helpers.h> 18 #include <string.h> 19 #include <utils.h> 20 21 22 /******************************************************************************* 23 * Context management library initialisation routine. This library is used by 24 * runtime services to share pointers to 'cpu_context' structures for the secure 25 * and non-secure states. Management of the structures and their associated 26 * memory is not done by the context management library e.g. the PSCI service 27 * manages the cpu context used for entry from and exit to the non-secure state. 28 * The Secure payload dispatcher service manages the context(s) corresponding to 29 * the secure state. It also uses this library to get access to the non-secure 30 * state cpu context pointers. 31 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 32 * which will used for programming an entry into a lower EL. The same context 33 * will used to save state upon exception entry from that EL. 34 ******************************************************************************/ 35 void cm_init(void) 36 { 37 /* 38 * The context management library has only global data to intialize, but 39 * that will be done when the BSS is zeroed out 40 */ 41 } 42 43 /******************************************************************************* 44 * The following function initializes the cpu_context 'ctx' for 45 * first use, and sets the initial entrypoint state as specified by the 46 * entry_point_info structure. 47 * 48 * The security state to initialize is determined by the SECURE attribute 49 * of the entry_point_info. The function returns a pointer to the initialized 50 * context and sets this as the next context to return to. 51 * 52 * The EE and ST attributes are used to configure the endianess and secure 53 * timer availability for the new execution context. 54 * 55 * To prepare the register state for entry call cm_prepare_el3_exit() and 56 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 57 * cm_e1_sysreg_context_restore(). 58 ******************************************************************************/ 59 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 60 { 61 unsigned int security_state; 62 uint32_t scr_el3, pmcr_el0; 63 el3_state_t *state; 64 gp_regs_t *gp_regs; 65 unsigned long sctlr_elx; 66 67 assert(ctx); 68 69 security_state = GET_SECURITY_STATE(ep->h.attr); 70 71 /* Clear any residual register values from the context */ 72 zeromem(ctx, sizeof(*ctx)); 73 74 /* 75 * SCR_EL3 was initialised during reset sequence in macro 76 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 77 * affect the next EL. 78 * 79 * The following fields are initially set to zero and then updated to 80 * the required value depending on the state of the SPSR_EL3 and the 81 * Security state and entrypoint attributes of the next EL. 82 */ 83 scr_el3 = read_scr(); 84 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 85 SCR_ST_BIT | SCR_HCE_BIT); 86 /* 87 * SCR_NS: Set the security state of the next EL. 88 */ 89 if (security_state != SECURE) 90 scr_el3 |= SCR_NS_BIT; 91 /* 92 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 93 * Exception level as specified by SPSR. 94 */ 95 if (GET_RW(ep->spsr) == MODE_RW_64) 96 scr_el3 |= SCR_RW_BIT; 97 /* 98 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 99 * Secure timer registers to EL3, from AArch64 state only, if specified 100 * by the entrypoint attributes. 101 */ 102 if (EP_GET_ST(ep->h.attr)) 103 scr_el3 |= SCR_ST_BIT; 104 105 #ifndef HANDLE_EA_EL3_FIRST 106 /* 107 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 108 * to EL3 when executing at a lower EL. When executing at EL3, External 109 * Aborts are taken to EL3. 110 */ 111 scr_el3 &= ~SCR_EA_BIT; 112 #endif 113 114 #ifdef IMAGE_BL31 115 /* 116 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as 117 * indicated by the interrupt routing model for BL31. 118 */ 119 scr_el3 |= get_scr_el3_from_routing_model(security_state); 120 #endif 121 122 /* 123 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 124 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 125 * next mode is Hyp. 126 */ 127 if ((GET_RW(ep->spsr) == MODE_RW_64 128 && GET_EL(ep->spsr) == MODE_EL2) 129 || (GET_RW(ep->spsr) != MODE_RW_64 130 && GET_M32(ep->spsr) == MODE32_hyp)) { 131 scr_el3 |= SCR_HCE_BIT; 132 } 133 134 /* 135 * Initialise SCTLR_EL1 to the reset value corresponding to the target 136 * execution state setting all fields rather than relying of the hw. 137 * Some fields have architecturally UNKNOWN reset values and these are 138 * set to zero. 139 * 140 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 141 * 142 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 143 * required by PSCI specification) 144 */ 145 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 146 if (GET_RW(ep->spsr) == MODE_RW_64) 147 sctlr_elx |= SCTLR_EL1_RES1; 148 else { 149 /* 150 * If the target execution state is AArch32 then the following 151 * fields need to be set. 152 * 153 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 154 * instructions are not trapped to EL1. 155 * 156 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 157 * instructions are not trapped to EL1. 158 * 159 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 160 * CP15DMB, CP15DSB, and CP15ISB instructions. 161 */ 162 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 163 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 164 } 165 166 /* 167 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 168 * and other EL2 registers are set up by cm_preapre_ns_entry() as they 169 * are not part of the stored cpu_context. 170 */ 171 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 172 173 if (security_state == SECURE) { 174 /* 175 * Initialise PMCR_EL0 for secure context only, setting all 176 * fields rather than relying on hw. Some fields are 177 * architecturally UNKNOWN on reset. 178 * 179 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 180 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 181 * that changes PMCCNTR_EL0[63] from 1 to 0. 182 * 183 * PMCR_EL0.DP: Set to one so that the cycle counter, 184 * PMCCNTR_EL0 does not count when event counting is prohibited. 185 * 186 * PMCR_EL0.X: Set to zero to disable export of events. 187 * 188 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 189 * counts on every clock cycle. 190 */ 191 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 192 | PMCR_EL0_DP_BIT) 193 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 194 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 195 } 196 197 /* Populate EL3 state so that we've the right context before doing ERET */ 198 state = get_el3state_ctx(ctx); 199 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 200 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 201 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 202 203 /* 204 * Store the X0-X7 value from the entrypoint into the context 205 * Use memcpy as we are in control of the layout of the structures 206 */ 207 gp_regs = get_gpregs_ctx(ctx); 208 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 209 } 210 211 /******************************************************************************* 212 * The following function initializes the cpu_context for a CPU specified by 213 * its `cpu_idx` for first use, and sets the initial entrypoint state as 214 * specified by the entry_point_info structure. 215 ******************************************************************************/ 216 void cm_init_context_by_index(unsigned int cpu_idx, 217 const entry_point_info_t *ep) 218 { 219 cpu_context_t *ctx; 220 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 221 cm_init_context_common(ctx, ep); 222 } 223 224 /******************************************************************************* 225 * The following function initializes the cpu_context for the current CPU 226 * for first use, and sets the initial entrypoint state as specified by the 227 * entry_point_info structure. 228 ******************************************************************************/ 229 void cm_init_my_context(const entry_point_info_t *ep) 230 { 231 cpu_context_t *ctx; 232 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 233 cm_init_context_common(ctx, ep); 234 } 235 236 /******************************************************************************* 237 * Prepare the CPU system registers for first entry into secure or normal world 238 * 239 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 240 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 241 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 242 * For all entries, the EL1 registers are initialized from the cpu_context 243 ******************************************************************************/ 244 void cm_prepare_el3_exit(uint32_t security_state) 245 { 246 uint32_t sctlr_elx, scr_el3, mdcr_el2; 247 cpu_context_t *ctx = cm_get_context(security_state); 248 249 assert(ctx); 250 251 if (security_state == NON_SECURE) { 252 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 253 if (scr_el3 & SCR_HCE_BIT) { 254 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 255 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 256 CTX_SCTLR_EL1); 257 sctlr_elx &= SCTLR_EE_BIT; 258 sctlr_elx |= SCTLR_EL2_RES1; 259 write_sctlr_el2(sctlr_elx); 260 } else if (EL_IMPLEMENTED(2)) { 261 /* 262 * EL2 present but unused, need to disable safely. 263 * SCTLR_EL2 can be ignored in this case. 264 * 265 * Initialise all fields in HCR_EL2, except HCR_EL2.RW, 266 * to zero so that Non-secure operations do not trap to 267 * EL2. 268 * 269 * HCR_EL2.RW: Set this field to match SCR_EL3.RW 270 */ 271 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 272 273 /* 274 * Initialise CPTR_EL2 setting all fields rather than 275 * relying on the hw. All fields have architecturally 276 * UNKNOWN reset values. 277 * 278 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 279 * accesses to the CPACR_EL1 or CPACR from both 280 * Execution states do not trap to EL2. 281 * 282 * CPTR_EL2.TTA: Set to zero so that Non-secure System 283 * register accesses to the trace registers from both 284 * Execution states do not trap to EL2. 285 * 286 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 287 * to SIMD and floating-point functionality from both 288 * Execution states do not trap to EL2. 289 */ 290 write_cptr_el2(CPTR_EL2_RESET_VAL & 291 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 292 | CPTR_EL2_TFP_BIT)); 293 294 /* 295 * Initiliase CNTHCTL_EL2. All fields are 296 * architecturally UNKNOWN on reset and are set to zero 297 * except for field(s) listed below. 298 * 299 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 300 * Hyp mode of Non-secure EL0 and EL1 accesses to the 301 * physical timer registers. 302 * 303 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 304 * Hyp mode of Non-secure EL0 and EL1 accesses to the 305 * physical counter registers. 306 */ 307 write_cnthctl_el2(CNTHCTL_RESET_VAL | 308 EL1PCEN_BIT | EL1PCTEN_BIT); 309 310 /* 311 * Initialise CNTVOFF_EL2 to zero as it resets to an 312 * architecturally UNKNOWN value. 313 */ 314 write_cntvoff_el2(0); 315 316 /* 317 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 318 * MPIDR_EL1 respectively. 319 */ 320 write_vpidr_el2(read_midr_el1()); 321 write_vmpidr_el2(read_mpidr_el1()); 322 323 /* 324 * Initialise VTTBR_EL2. All fields are architecturally 325 * UNKNOWN on reset. 326 * 327 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 328 * 2 address translation is disabled, cache maintenance 329 * operations depend on the VMID. 330 * 331 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 332 * translation is disabled. 333 */ 334 write_vttbr_el2(VTTBR_RESET_VAL & 335 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 336 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 337 338 /* 339 * Initialise MDCR_EL2, setting all fields rather than 340 * relying on hw. Some fields are architecturally 341 * UNKNOWN on reset. 342 * 343 * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical 344 * profiling controls to EL2. 345 * 346 * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in non-secure 347 * state. Accesses to profiling buffer controls at 348 * non-secure EL1 are not trapped to EL2. 349 * 350 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 351 * EL1 System register accesses to the Debug ROM 352 * registers are not trapped to EL2. 353 * 354 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 355 * System register accesses to the powerdown debug 356 * registers are not trapped to EL2. 357 * 358 * MDCR_EL2.TDA: Set to zero so that System register 359 * accesses to the debug registers do not trap to EL2. 360 * 361 * MDCR_EL2.TDE: Set to zero so that debug exceptions 362 * are not routed to EL2. 363 * 364 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 365 * Monitors. 366 * 367 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 368 * EL1 accesses to all Performance Monitors registers 369 * are not trapped to EL2. 370 * 371 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 372 * and EL1 accesses to the PMCR_EL0 or PMCR are not 373 * trapped to EL2. 374 * 375 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 376 * architecturally-defined reset value. 377 */ 378 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 379 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 380 >> PMCR_EL0_N_SHIFT)) & 381 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 382 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 383 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 384 | MDCR_EL2_TPMCR_BIT)); 385 386 #if ENABLE_SPE_FOR_LOWER_ELS 387 uint64_t id_aa64dfr0_el1; 388 389 /* Detect if SPE is implemented */ 390 id_aa64dfr0_el1 = read_id_aa64dfr0_el1() >> 391 ID_AA64DFR0_PMS_SHIFT; 392 if ((id_aa64dfr0_el1 & ID_AA64DFR0_PMS_MASK) == 1) { 393 /* 394 * Make sure traps to EL2 are not generated if 395 * EL2 is implemented but not used. 396 */ 397 mdcr_el2 &= ~MDCR_EL2_TPMS; 398 mdcr_el2 |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); 399 } 400 #endif 401 402 write_mdcr_el2(mdcr_el2); 403 404 /* 405 * Initialise HSTR_EL2. All fields are architecturally 406 * UNKNOWN on reset. 407 * 408 * HSTR_EL2.T<n>: Set all these fields to zero so that 409 * Non-secure EL0 or EL1 accesses to System registers 410 * do not trap to EL2. 411 */ 412 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 413 /* 414 * Initialise CNTHP_CTL_EL2. All fields are 415 * architecturally UNKNOWN on reset. 416 * 417 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 418 * physical timer and prevent timer interrupts. 419 */ 420 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 421 ~(CNTHP_CTL_ENABLE_BIT)); 422 } 423 } 424 425 cm_el1_sysregs_context_restore(security_state); 426 cm_set_next_eret_context(security_state); 427 } 428 429 /******************************************************************************* 430 * The next four functions are used by runtime services to save and restore 431 * EL1 context on the 'cpu_context' structure for the specified security 432 * state. 433 ******************************************************************************/ 434 void cm_el1_sysregs_context_save(uint32_t security_state) 435 { 436 cpu_context_t *ctx; 437 438 ctx = cm_get_context(security_state); 439 assert(ctx); 440 441 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 442 el1_sysregs_context_save_post_ops(); 443 444 #if IMAGE_BL31 445 if (security_state == SECURE) 446 PUBLISH_EVENT(cm_exited_secure_world); 447 else 448 PUBLISH_EVENT(cm_exited_normal_world); 449 #endif 450 } 451 452 void cm_el1_sysregs_context_restore(uint32_t security_state) 453 { 454 cpu_context_t *ctx; 455 456 ctx = cm_get_context(security_state); 457 assert(ctx); 458 459 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 460 461 #if IMAGE_BL31 462 if (security_state == SECURE) 463 PUBLISH_EVENT(cm_entering_secure_world); 464 else 465 PUBLISH_EVENT(cm_entering_normal_world); 466 #endif 467 } 468 469 /******************************************************************************* 470 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 471 * given security state with the given entrypoint 472 ******************************************************************************/ 473 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 474 { 475 cpu_context_t *ctx; 476 el3_state_t *state; 477 478 ctx = cm_get_context(security_state); 479 assert(ctx); 480 481 /* Populate EL3 state so that ERET jumps to the correct entry */ 482 state = get_el3state_ctx(ctx); 483 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 484 } 485 486 /******************************************************************************* 487 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 488 * pertaining to the given security state 489 ******************************************************************************/ 490 void cm_set_elr_spsr_el3(uint32_t security_state, 491 uintptr_t entrypoint, uint32_t spsr) 492 { 493 cpu_context_t *ctx; 494 el3_state_t *state; 495 496 ctx = cm_get_context(security_state); 497 assert(ctx); 498 499 /* Populate EL3 state so that ERET jumps to the correct entry */ 500 state = get_el3state_ctx(ctx); 501 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 502 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 503 } 504 505 /******************************************************************************* 506 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 507 * pertaining to the given security state using the value and bit position 508 * specified in the parameters. It preserves all other bits. 509 ******************************************************************************/ 510 void cm_write_scr_el3_bit(uint32_t security_state, 511 uint32_t bit_pos, 512 uint32_t value) 513 { 514 cpu_context_t *ctx; 515 el3_state_t *state; 516 uint32_t scr_el3; 517 518 ctx = cm_get_context(security_state); 519 assert(ctx); 520 521 /* Ensure that the bit position is a valid one */ 522 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 523 524 /* Ensure that the 'value' is only a bit wide */ 525 assert(value <= 1); 526 527 /* 528 * Get the SCR_EL3 value from the cpu context, clear the desired bit 529 * and set it to its new value. 530 */ 531 state = get_el3state_ctx(ctx); 532 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 533 scr_el3 &= ~(1 << bit_pos); 534 scr_el3 |= value << bit_pos; 535 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 536 } 537 538 /******************************************************************************* 539 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 540 * given security state. 541 ******************************************************************************/ 542 uint32_t cm_get_scr_el3(uint32_t security_state) 543 { 544 cpu_context_t *ctx; 545 el3_state_t *state; 546 547 ctx = cm_get_context(security_state); 548 assert(ctx); 549 550 /* Populate EL3 state so that ERET jumps to the correct entry */ 551 state = get_el3state_ctx(ctx); 552 return read_ctx_reg(state, CTX_SCR_EL3); 553 } 554 555 /******************************************************************************* 556 * This function is used to program the context that's used for exception 557 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 558 * the required security state 559 ******************************************************************************/ 560 void cm_set_next_eret_context(uint32_t security_state) 561 { 562 cpu_context_t *ctx; 563 564 ctx = cm_get_context(security_state); 565 assert(ctx); 566 567 cm_set_next_context(ctx); 568 } 569
