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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
      4  */
      5 #ifndef _ASM_ARCH_GRF_RK322X_H
      6 #define _ASM_ARCH_GRF_RK322X_H
      7 
      8 #include <common.h>
      9 
     10 struct rk322x_grf {
     11 	unsigned int gpio0a_iomux;
     12 	unsigned int gpio0b_iomux;
     13 	unsigned int gpio0c_iomux;
     14 	unsigned int gpio0d_iomux;
     15 
     16 	unsigned int gpio1a_iomux;
     17 	unsigned int gpio1b_iomux;
     18 	unsigned int gpio1c_iomux;
     19 	unsigned int gpio1d_iomux;
     20 
     21 	unsigned int gpio2a_iomux;
     22 	unsigned int gpio2b_iomux;
     23 	unsigned int gpio2c_iomux;
     24 	unsigned int gpio2d_iomux;
     25 
     26 	unsigned int gpio3a_iomux;
     27 	unsigned int gpio3b_iomux;
     28 	unsigned int gpio3c_iomux;
     29 	unsigned int gpio3d_iomux;
     30 
     31 	unsigned int reserved1[4];
     32 	unsigned int con_iomux;
     33 	unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
     34 	unsigned int gpio0_p[4];
     35 	unsigned int gpio1_p[4];
     36 	unsigned int gpio2_p[4];
     37 	unsigned int gpio3_p[4];
     38 	unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
     39 	unsigned int gpio0_e[4];
     40 	unsigned int gpio1_e[4];
     41 	unsigned int gpio2_e[4];
     42 	unsigned int gpio3_e[4];
     43 	unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
     44 	unsigned int soc_con[7];
     45 	unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
     46 	unsigned int soc_status[3];
     47 	unsigned int chip_id;
     48 	unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
     49 	unsigned int cpu_con[4];
     50 	unsigned int reserved7[4];
     51 	unsigned int cpu_status[2];
     52 	unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
     53 	unsigned int os_reg[8];
     54 	unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
     55 	unsigned int ddrc_stat;
     56 	unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
     57 	unsigned int sig_detect_con[2];
     58 	unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
     59 	unsigned int sig_detect_status[2];
     60 	unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
     61 	unsigned int sig_detect_clr[2];
     62 	unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
     63 	unsigned int emmc_det;
     64 	unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
     65 	unsigned int host0_con[3];
     66 	unsigned int reserved15;
     67 	unsigned int host1_con[3];
     68 	unsigned int reserved16;
     69 	unsigned int host2_con[3];
     70 	unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
     71 	unsigned int usbphy0_con[27];
     72 	unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
     73 	unsigned int usbphy1_con[27];
     74 	unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
     75 	unsigned int otg_con0;
     76 	unsigned int uoc_status0;
     77 	unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
     78 	unsigned int mac_con[2];
     79 	unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
     80 	unsigned int macphy_con[4];
     81 	unsigned int macphy_status;
     82 };
     83 check_member(rk322x_grf, ddrc_stat, 0x604);
     84 
     85 struct rk322x_sgrf {
     86 	unsigned int soc_con[11];
     87 	unsigned int busdmac_con[4];
     88 };
     89 
     90 /* GRF_MACPHY_CON0 */
     91 enum {
     92 	MACPHY_CFG_ENABLE_SHIFT = 0,
     93 	MACPHY_CFG_ENABLE_MASK  = 1 << MACPHY_CFG_ENABLE_SHIFT,
     94 };
     95 #endif
     96